Principal RFIC PLL Design Engineer

Quick Facts

• Role: Lead PLL design for advanced CMOS/SiGe space communication systems
• Focus: RF/mmWave high-speed (>20 GHz) PLL performance optimization

Description

Lead the design, development, and integration of phase-locked loops (PLLs) in advanced CMOS/SiGe technologies to deliver state-of-the-art performance for space communication systems. Use Spectre and AMS mixed-signal flows to optimize performance trade-offs, and collaborate with RF system architects and verification teams through layout, tape-out, and test bring-up. Contribute analog/RF building blocks and mentor engineers in analog design best practices.

Responsibilities

• Lead PLL design, development, and integration in advanced CMOS and SiGe
• Optimize performance trade-offs across mmWave/RF requirements
• Use Spectre and AMS flows to develop high-performance PLL circuits
• Collaborate with RF system architects on PLL and sub-block requirements
• Oversee layout, top-level integration, floorplanning, and verification for tape-out
• Develop test plans, support bring-up, optimize performance, and improve yield
• Investigate and implement analog building blocks to enhance circuit performance and mentor junior engineers

Requirements

• MS or PhD in Electrical Engineering or a related technical discipline
• 10+ years of experience designing high-speed (>20 GHz) PLLs for RF/mmWave
• Proficiency in mixed-mode and RF modeling, simulation, and verification
• Experience with Spectre and AMS flows
• Extensive experience in PLL silicon characterization and debugging
• Strong knowledge of analog/RF building blocks (amplifiers, filters, mixers)

Benefits

Opportunity to advance PLL technology for space-based connectivity and mission-critical RF systems.