Senior Manager, Silicon Speed Productization (Silicon Co-Design)

Quick Facts

• Role: Senior Manager, Silicon Speed Productization

Description

Own the prediction-to-silicon speed correlation loop to ensure products deliver intended frequency across voltage, process, temperature, workload, and lifetime conditions. Lead root-cause closure for the hardest speed failures, and translate evidence into product limits, guardbands, binning, aging, and production sign-off criteria. Scale closed-loop, automation, and AI-assisted workflows that improve analysis coverage and cycle time, while leading a globally distributed team.

Responsibilities

• Close the simulation-to-silicon speed correlation loop from pre-silicon planning and first power-on through production sign-off for GPU, CPU, and SoC programs

• Drive root-cause closure when frequency corners fail, minimum operating voltage is too high, timing escapes analysis, or workload behavior diverges from models

• Define product limits with evidence: silicon margining, PVT characterization, guardbanding, aging, and speed binning; translate results into product requirements and production decisions

• Left-shift learning by feeding measured silicon insights back into timing models, critical-path predictions, test content, design practices, and future architectures

• Convert characterization data, model deltas, yield trends, and speed risks into decision-ready options for leadership

• Build and scale closed-loop data, automation, and AI-assisted workflows for test orchestration, anomaly detection, triage, and reporting

• Hire, develop, and retain a high-performing team; grow engineers into subsystem experts and first-line managers into independent leaders

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering (or equivalent experience)

• 12+ overall years of experience in silicon characterization, post-silicon validation, timing or performance analysis, including 5+ years leading technical teams

• Proven management experience developing senior engineers and first-line managers

• Deep foundation in digital design, computer architecture, static timing analysis, critical-path behavior, clocking, power/timing interactions, semiconductor process variation, sampling, and statistics

• Hands-on expertise in silicon speed characterization, simulation-to-silicon correlation, voltage-frequency margining, guardbanding, and PVT plus binning dependencies

• Demonstrated ability to drive ambiguous, system-level issues to root-cause closure

• Data-analysis and automation proficiency (e.g., Python, JMP, SQL) with judgment to distinguish correlation from causation

• Strong written and verbal communication to translate complex technical issues into decision-ready options

Benefits

• Base salary range: 232,000 USD – 368,000 USD (determined by location and experience)

• Eligible for equity and benefits