Design-for-Test (DFT) Engineer — ASIC Backend

Quick Facts

• Role: Design-for-Test (DFT) Engineer — ASIC Backend

• Experience levels: Associate to Lead (Jr → Principal)

• Work model: 100% onsite; 1st shift

• Locations: El Segundo, CA or Huntington Beach, CA

• Security: U.S. Secret clearance required post-start; U.S. citizenship required

Description

Join the DFT team driving architecture, verification, and post-silicon validation for leading-edge ASICs. You will design and validate test access mechanisms—such as TAP/JTAG, IJTAG (IEEE 1687), boundary scan, MBIST, and scan compression—and lead ATPG pattern generation, coverage optimization, memory test validation, and silicon debug. The role includes integration of DFT features across the chip design flow and collaboration with cross-functional and external partners when needed.

Responsibilities

• Design and implement DFT architectures: TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (BSCAN), MBIST, and scan compression
• Develop and validate TAP/JTAG and IJTAG infrastructures, BSDL/ICL/PDL artifacts, and ATPG pattern generation
• Drive pattern generation, coverage optimization, memory test validation, and silicon debug (scan, at-speed, bring-up)
• Integrate DFT features across the chip design flow; collaborate with cross-functional teams to ensure robust DFT integration
• Coordinate with external partners/customers on custom DFT interfaces and security requirements when applicable
• Develop and deploy DFT methodologies for next-generation products
• Occasional travel and after-hours meetings during critical milestones

Requirements

• Ability to obtain a U.S. Security Clearance; U.S. citizenship required
• Interim and/or final U.S. Secret Clearance post-start
• Bachelor of Science in a related field (Engineering, Computer Science, Data Science, Mathematics, Physics, Chemistry) or non-US equivalent
• 2+ years of DFT experience (experience level adjusted by role)
• Strong ASIC/logic design flow knowledge and HDL (Verilog/SystemVerilog)
• Static timing analysis and ECO process knowledge
• Hands-on DFT experience with TAP/JTAG, IJTAG (IEEE 1687), Boundary Scan (IEEE 1149.1), MBIST, scan compression, ATPG, at-speed test, and silicon debug
• Proficiency in scripting (Tcl/Perl/Python) and DFT verification methodologies
• Excellent analytical, problem-solving, and communication skills

Benefits

• Competitive base pay and variable compensation opportunities
• Health insurance, flexible spending accounts, health savings accounts, retirement savings plans
• Life and disability insurance programs
• Programs providing paid and unpaid time away from work (eligibility varies)
• Relocation support based on candidate eligibility