Sr. Manager Silicon Design Engineering

🏢 Summary: Staff CAD Engineer role focused on architecting, developing, and deploying the CI2 silicon design environment for next-generation TPU and AI/ML hardware. The position improves silicon development flows, iteration speed, and power, performance, cost, and quality outcomes through advanced tooling and cross-functional collaboration. 🗂️ Requirements: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, related field, or equivalent practical experience, 10 years of technical leadership experience in critical silicon-design areas, Experience in at least two silicon disciplines, Experience developing and deploying advanced tools and development flows for the silicon lifecycle, Ability to lead design-environment architecture, development, and deployment, Knowledge of silicon development phases and scalable design flows 📃 Skills: Silicon, TPU, CI2, AI/ML, DFT, Synthesis, Verification, Firmware, Architecture, Modeling, Place-and-route, Timing, APIs 🏢 Description: Minimum qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. • 10 years of experience in technical leadership focusing on one or more critical aspects of silicon design. • Experience in two or more silicon disciplines, including architecture modeling, logic design, functional verification, DFT, synthesis, place and route, timing analysis, physical verification, or firmware development. • Experience developing and deploying advanced tools and development flows that streamline the silicon lifecycle and improve engineering productivity. Preferred qualifications • Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture. • 15 years of relevant academic and industrial experience in advanced silicon development. • Experience identifying the need for a silicon methodology change, developing a solution, and successfully deploying it with impact to more than 25 developers. • Experience developing solutions that require bridging knowledge gaps among collaborators. • Experience collaborating in internal or external ecosystem standardization efforts. • Knowledge of both front-end silicon development processes—architecture, logic design, and verification—and back-end processes—logic synthesis, place and route, timing convergence, and physical verification. About the job Shape the future of AI/ML hardware acceleration by driving TPU technology for demanding AI/ML applications. Develop custom silicon solutions and use design and verification expertise to verify complex digital designs, with a focus on TPU architecture and its integration within AI/ML-driven systems. As a Staff CAD Engineer, Silicon Design Environment, collaborate with domain experts across the silicon development spectrum to deliver the development environment for chips powering next-generation cloud systems. Refine ambiguous intent into solutions and rally others to develop or deploy them. Responsibilities • Use knowledge of silicon development phases to define the architecture and lead the development and deployment of the overall CI2 design environment as a coherent system of first-party and third-party tools, industry-standard and internal APIs/data formats, and scalable design flows. • Collaborate with technical leaders across CI2 sites to identify evolutionary and revolutionary tooling and methodology changes that enable convergence on a shared design environment. • Engage with other internal teams to keep CI2 at the forefront of advanced silicon development. • Ensure developed technologies optimize project iteration speed while achieving planned power, performance, cost, and quality metrics. • Partner with tools and methodologies team members to apply procedural and AI-first approaches that improve efficiency.

🏢 Summary: Lead a hands-on full-stack/backend engineering effort to build scalable services, APIs, workflow engines, and agentic AI systems for logistics optimization. The role combines technical leadership, production reliability, third-party integrations, and mentoring while delivering AI-driven planning and optimization capabilities. 🗂️ Requirements: Senior or technical-lead backend engineering experience, Strong Python and API-development proficiency, Scalable distributed-systems architecture experience, API design, data modeling, and integration expertise, Agentic AI, LLM orchestration, RAG, or multi-agent systems experience, Cloud-platform and CI/CD experience, Third-party API integration experience, Production debugging experience with LLM-driven systems, Engineering mentorship and code/design review experience, Technical leadership and stakeholder communication skills, Successful pre-employment screening 📃 Skills: Python, FastAPI, TypeScript, LangGraph, LangChain, RAG, AWS, Bedrock, GitLab, CICD, SSE, WebSockets, LLM 🏢 Description: What's the role? We are looking for a Tech Lead Fullstack Engineer to build core backend systems powering next-generation agentic AI solutions for the logistics industry. The systems developed by this team optimize deliveries at scale improving driver efficiency, increasing reliability, reducing operational costs, and lowering environmental impact. In this role, you will focus on building the core service layer, customer-facing APIs, workflow engines, and integrations with HERE APIs and third-party systems that enable intelligent logistics workflows. You will work closely with senior engineers and technical leaders to design and implement scalable, reliable systems that support AI-driven planning and optimization use cases. This is a hands-on engineering role with a strong focus on backend development, system reliability, and production-quality delivery . What You’ll Do: Lead the design, build, and maintenance of core backend services, APIs, and workflow orchestration systems for logistics applications Drive integrations with HERE APIs and external third-party systems to support real-world logistics workflows Translate ambiguous product and technical requirements into scalable, maintainable system components, and help others on the team do the same Write clean, efficient, and well-tested code in Python and/or TypeScript, setting the standard for code quality across the team Design and build agentic AI systems based on LangGraph, and help shape how the team approaches LLM orchestration and multi-agent architecture Lead system design discussions and own key architectural decisions, ensuring solutions align with the overall system vision Build and maintain customer-facing APIs with a strong focus on usability, performance, and reliability Ensure high-quality delivery through testing, monitoring, and debugging in production environments, including systems with non-deterministic (LLM-driven) behavior Mentor engineers through code review, design feedback, and pairing, and help grow the team's technical capabilities Collaborate with engineers, product managers, and domain experts to deliver end-to-end features Continuously improve system performance, scalability, and operational efficiency Leverage AI-assisted development tools to improve development speed and code quality Who are you? What We’re Looking For: Proven experience as a technical lead or in a senior engineering role, with strong backend development skills and a track record of owning systems end-to-end Strong proficiency in Python, with experience building APIs (FastAPI or similar) and backend systems; TypeScript is a plus Experience architecting scalable services and distributed systems, and making tradeoff decisions that hold up under real-world load and change Strong command of API design, data modeling, and system integration patterns — ideally including streaming/event-driven APIs (e.g., SSE, websockets), not just request/response Hands-on experience building or leading development of agentic AI systems: LLM orchestration frameworks (e.g., LangGraph, LangChain), RAG pipelines, or multi-agent architectures Experience working with cloud platforms, ideally AWS (including managed LLM services like Bedrock), and modern CI/CD practices (GitLab CI or equivalent) Experience integrating with external/third-party APIs and handling real-world data and system constraints in production Strong debugging and problem-solving skills in production environments, including systems with non-deterministic (LLM-driven) components Experience mentoring engineers, conducting code/design reviews, and raising the technical bar across a team Ability to break down ambiguous problems into well-defined work, balancing hands-on coding with technical leadership Excellent communication skills, with the ability to align engineering decisions with product and business priorities, and a pragmatic approach to engineering challengesWe are looking for a Lead Software Engineer to build core backend systems powering next-generation agentic AI solutions for the logistics industry. The systems developed by this team optimize deliveries at scale improving driver efficiency, increasing reliability, reducing operational costs, and lowering environmental impact.Design , build, and maintain What We Offer: The opportunity to tackle meaningful and challenging problems A chance to continuously learn and stay on top of the latest technology trends Work that has real-world impact, shaping the future of mobility and technology Regular feedback to help you grow and succeed in your role A collaborative and supportive team environment where your contributions are valued Competitive salary plus bonus Flexible working hours and a hybrid working environment Medical coverage for you and your family This role is eligible for Creative Tax Incentive scheme in Poland” or KUP (Autorskie Koszty Uzyskania Przychodu) Option to work on a B2B contract (please note: benefits, bonus and KUP do not apply in this case) Change is HERE. Apply Now! #LI-AK8   #LI-HYBRID Life at HERE in Poland comes with a competitive total rewards package designed to support your health, wellbeing, and performance. This includes a base salary, a Short-Term Incentive (STI) bonus (percentage based on role), a creative tax advantage for eligible positions, private medical care (including dental), life insurance, a meal allowance, vision reimbursement, a remote work allowance (if applicable), access to MyBenefit and Multisport programs, and various wellbeing initiatives. Paid time off, sick leave, and parental leave are provided in accordance with the Polish Labor Code. As part of HERE Technologies employment process, candidates will be required to successfully complete a pre-employment screening process. This offer and any related claims are subject to the successful completion of a pre-employment screening. This will involve employment, education, and criminal verification if applicable. HERE is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, age, gender identity, sexual orientation, marital status, parental status, religion, sex, national origin, disability, veteran status, and other legally protected characteristics. Who are we? HERE Technologies is a location data and technology platform company. We empower our customers to achieve better outcomes – from helping a city manage its infrastructure or a business optimize its assets to guiding drivers to their destination safely. At HERE we take it upon ourselves to be the change we wish to see. We create solutions that fuel innovation, provide opportunity and foster inclusion to improve people’s lives. If you are inspired by an open world and driven to create positive change, join us. Learn more about us on our YouTube Channel. Apply for this job online Email this job to a friend Share on your newsfeed Connect With Us! Not ready to apply? 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🏢 Summary: Senior Application Security Engineer role focused on building automated security controls across the SDLC for a large-scale financial services program. The position centers on Python-based security automation, AI-enabled code scanning, CI/CD security integration, and code-level remediation guidance, with autonomous execution. 🗂️ Requirements: 5+ years of software engineering experience, Python proficiency for security automation and scripting, Application Security or DevSecOps experience, Autonomous execution without daily supervision, Upper-intermediate English 📃 Skills: Python, DevSecOps, AppSec, SAST, DAST, SCA, CI/CD, Java, LLMs 🏢 Description: ID71672 AgileEngine is an Inc. 5000 company that creates award-winning software for Fortune 500 brands and trailblazing startups across 17+ industries. We rank among the leaders in areas like application development and AI/ML, and our people-first culture has earned us multiple Best Place to Work awards. Why join us If you're looking for a place to grow, make an impact, and work with people who care, we'd love to meet you! :) About the role We are looking for a Senior Application Security Engineer to architect and build automated security layers within the SDLC, engineering AI-enabled secure code scanning, hardened baseline automation, and CI/CD security tooling integration within a large-scale financial services program. You will work primarily in Python to build automated security runbooks, deploy and tune scanning tools, and provide code-level remediation guidance to development teams — operating with full autonomy and no daily supervision. AppSec and DevSecOps experience is strongly preferred; SAST/DAST/SCA and Java expertise are a plus. What you will do Engineer and deploy AI-enabled secure code scanning capabilities and "Golden Images" to drive secure-from-the-start adoption; Automate the development of secure coding patterns and integrate them with traditional and Agentic SDLC workflows; Architect the integration of continuous security scanning tools (SAST, DAST, SCA) into enterprise CI/CD pipelines, tuning them to eliminate noise; Act as a senior technical SME, reading and reviewing complex application code (Java/Python) to provide software engineers with highly specific, code-level remediation guidance. Must haves 5+ years of software engineering experience, ideally with a focus on Application Security and DevSecOps; Strong coding and architectural proficiency in Python for security automation and scripting; Fully autonomous execution capability, requiring no daily supervision to map out and build automated security runbooks; Upper-intermediate English level. Nice to haves Deep, hands-on expertise deploying and tuning modern application security testing tools, including SAST, DAST, and SCA, and integrating them into complex CI/CD orchestration ecosystems; Experience integrating LLMs, AI agents, or automated coding assistants to streamline vulnerability triaging or secure code generation; Advanced application threat modeling experience; Ability to confidently read, review, and secure enterprise source Java code. The benefits of joining us Professional growth Accelerate your professional journey with mentorship, TechTalks, and personalized growth roadmaps Competitive compensation We match your ever-growing skills, talent, and contributions with competitive USD-based compensation and budgets for education, fitness, and team activities A selection of exciting projects Join projects with modern solutions development and top-tier clients that include Fortune 500 enterprises and leading product brands Flextime Tailor your schedule for an optimal work-life balance, by having the options of working from home and going to the office – whatever makes you the happiest and most productive. Meet Our Recruitment Process Asynchronous stage – An automated, self-paced track that helps us move faster and give you quicker feedback: Short online form to confirm basic requirements 30–60 minute skills assessment via Codility – a platform founded in Poland that helps us provide quicker feedback and streamline this stage of the process. 5-minute introduction video Synchronous stage – Live interviews Technical interview with our engineering team (scheduled at your convenience) Final interview with your future teammates If it’s a match — you’ll get an offer!

🏢 Summary: Executive leadership role directing the multi-year architecture roadmap and commercialization of future Tensor SoCs and chipsets for battery-powered devices. The position leads a global architecture organization, drives hardware-software innovation for performance, power, and cost, and shapes flagship-device experiences including imaging and on-device GenAI. 🗂️ Requirements: Bachelor’s degree in Electrical Engineering, Computer Science, related field, or equivalent practical experience, 20 years of SoC system architecture and hardware/software co-design experience for battery-powered devices, Track record of driving SoC architecture changes that improve power, performance, or cost, 15 years of people-management experience, Experience leading multiple functional groups or a silicon design/architecture organization, Experience commercializing SoC architecture changes and related software 📃 Skills: SoC, Silicon, Codesign, Architecture, Chipsets, Hardware, Software, Tensor, Power, Performance 🏢 Description: Minimum qualifications • Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience. • 20 years of experience in SoC system architecture and hardware/software co-design for battery-powered devices, driving SoC architecture changes for battery-powered devices to achieve improvement in power, performance, or cost. • 15 years of experience in people management, including experience leading multiple functional groups or a silicon design/architecture organization. • Experience with the commercialization of architecture changes (i.e., SoC and related software), not just evaluation and recommendations. Preferred qualifications • Master's degree or PhD in Electrical Engineering, Computer Science, or a related field. • 20 years of experience with silicon system architecture or custom silicon design on process nodes in foundries. • Experience analyzing high-stakes workloads (e.g., GenAI, imaging, computer vision) and defining hardware-software boundaries (e.g., firmware, OS drivers, kernel virtualization). • Excellent change-management and operational leadership skills, with experience driving systemic organizational change or merging large engineering teams across global sites. • Technical knowledge of high-performance coherent fabrics, memory subsystems, and core IPs, including CPU, GPU, TPU, camera, and system security blocks. Description As Senior Director of the Chipset and System-on-a-Chip (SoC) Architecture Team, you will be responsible for exploring, owning, and executing the architecture for future Tensor SoCs and chipsets. You will lead a consolidated organization of full-time employees whose primary mandate is to explore, analyze, and make recommendations on architecture options and innovations for future SoCs and chipsets, including memory architecture and chipsets; identify and drive new system-level features across a cross-functional organization for performance and power optimization of critical user journeys; and ensure all architectural innovations are driven to commercialization. In this role, you will hold decision-making autonomy over SoC and chipset architecture exploration, analysis, recommendations, and commercialization. The role requires the ability to make high-level trade-offs that drive system-level hardware and software innovation. You will directly impact the competitiveness of flagship devices by anticipating technology trends and preparing Tensor architecture for future critical user journeys, particularly imaging, GenAI, and Gemini use cases. You will ensure future silicon generations are optimized for performance, power, and cost, especially for first-party use cases, while preventing costly silicon-area inflation and unproductized hardware blocks. You will direct a geographically distributed, vertically integrated organization across Mountain View, Bangalore, and Taiwan. Responsibilities • Lead the multi-year silicon system architecture roadmap for future Tensor SoCs. • Establish and enforce a directed innovation model in which all hardware and IP innovations have explicit software sponsorship. • Lead and scale a multi-disciplinary, geographically distributed organization of full-time employees across three core pillars. • Provide mentorship, professional development, and strategic management to a team of senior leaders. • Integrate merged organizations and establish clear operational boundaries with implementation and IP core teams. • Collaborate closely to set strict system target boundaries, including chassis, power, limits, and performance, without displacing execution-level block architects. • Serve as the lead technical and strategic liaison to executive leadership.

🏢 Summary: Senior Hardware Design Engineer role focused on defining, designing, validating, and optimizing next-generation machine-learning chips, cards, and server integrations for large-scale data centers. The position leads PCIe and SerDes design topics and drives hardware performance, quality, and cost improvements. 🗂️ Requirements: Bachelor’s degree in Electrical Engineering or related field, Debugging experience across architecture, algorithms, functionality, and performance, Multi-level logic verification experience from IP blocks and SoCs through full-system testing 📃 Skills: PCIe, SerDes, SoC, IP, debugging, verification, hardware, ML 🏢 Description: Description Design, define, validate, and optimize next-generation machine-learning chips, cards, and server integrations for large-scale data centers. As a senior hardware team member, participate in the design and execution of PCIe and SerDes topics to create customized platforms for data-center technology. As part of the Machine Learning Acceleration team, lead the application of new technologies to large-scale server deployments. Improve product performance, quality, and cost while collaborating with thought leaders across technology areas. Basic Qualifications • Bachelor’s degree in Electrical Engineering or a related field • Experience identifying bugs in architecture, algorithms, functionality, and performance, with strong overall debugging skills • Experience verifying multiple levels of logic, from IP blocks to SoCs to full-system testing Preferred Qualifications • Master’s degree in Electrical or Communications Engineering or a related field • Experience with formal verification techniques, including abstraction and end-to-end checking • Experience with ARM and various DSP ISAs • Experience with current and upcoming RF standards in cellular (4G/5G NR), WiMAX, 802.11ad, microwave backhaul, or related broadband wireless standards • Experience with industry-standard tools and scripting languages, including Python or Perl, for automation Compensation and Benefits The compensation package includes sign-on payments and restricted stock units (RSUs). Final compensation is determined by experience, qualifications, and location. Annual base salary ranges: • Cupertino, CA: $157,300–$212,800 USD • Austin, TX: $136,000–$184,000 USD Comprehensive benefits include medical, dental, vision, prescription, life and AD&D insurance options, employee assistance and mental-health support, flexible spending accounts, adoption and surrogacy reimbursement coverage, 401(k) matching, paid time off, and parental leave.