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October 23, 2026

Senior FPGA Prototyping Engineer (Hardware)

Senior • On-site

165,000 - 310,000 USD/yr

Santa Clara, CA

Description

A Senior FPGA Prototyping Engineer to build and bring up FPGA prototypes for next-generation GPUs and SoCs, enabling faster and more efficient prototyping. You will take designs from RTL preparation through backend implementation, timing closure, bitstream generation, and FPGA platform bring-up, then support customer releases and issues. This role requires strong cross-team coordination and advanced debugging.

Role Description

Build and deliver FPGA prototypes by preparing RTL for FPGA, partitioning the design, and running synthesis and place-and-route. Analyze timing, improve performance, generate bitstreams, and verify correctness through bring-up and testing infrastructure.

Responsibilities

  • Make RTL FPGA-friendly, partition the design, and run synthesis through place-and-route.
  • Analyze timing, improve prototype performance, and generate bitstreams.
  • Bring up designs on FPGA prototyping platforms and resolve sophisticated debugging issues.
  • Release prototypes to customers and support them when problems occur.
  • Define configurations, develop/modify bring-up and testing infrastructure, and verify design correctness.
  • Coordinate with architects, designers, verification engineers, and software teams.

Requirements

  • BS (or equivalent) in Electrical Engineering, Computer Engineering, or related field with 12+ years of experience in FPGA prototyping, or MS with 10+ years of proven FPGA prototyping experience.
  • Good understanding of FPGA prototyping architecture, devices, flows, and tools.
  • Experience with backend FPGA prototyping flows: synthesis, place-and-route, and timing closure.
  • Experience emphasizing Synopsys Protocompiler or Siemens VPS and Xilinx Vivado.
  • Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB).
  • Knowledge of Verilog and SystemVerilog plus digital design concepts.
  • Strong debugging and problem-solving skills.
  • Hands-on lab FPGA debug methodologies and tools (Identify or ChipScope) and lab debug equipment (oscilloscopes, logic analyzers).

Benefits

  • Base salary range: $196,000–$310,500 (Level 5) or $232,000–$368,000 (Level 6), based on location and experience.
  • Eligible for equity and benefits.

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