Systems Engineer, Digital Payload

Quick Facts

Experienced Digital Payload Systems Engineer providing end-to-end technical leadership for complex digital space systems; site-based role with 3+ days (60%+) per week from a company office or work location.

Description

Provide technical leadership for complex digital space systems by owning digital payload architecture, system performance, requirements, technical budgets, verification strategy, and long-term payload evolution. Serve as a senior technical authority across FPGA and ASIC based digital systems, independently defining complex problems, driving architecture decisions, coordinating cross-functional execution, and mentoring other engineers. Influence technical outcomes across programs without direct authority.

Responsibilities

• Own end-to-end digital payload system performance, architecture, requirements, and verification strategy.
• Lead architecture definition and trade studies for FPGA, ASIC, DSP, high-speed I/O, clocking, and payload processing systems.
• Define and resolve complex system-level problems across hardware, firmware, software, RF, integration, and test teams.
• Drive design decisions for beamforming, channelization, regenerative payloads, and standards-based implementations including DVB-S2, DVB-S2X, DVB-RCS, and 3GPP.
• Own technical budgets, margin posture, assumptions, risks, and analytical models supporting program decisions.
• Develop and maintain key technical artifacts, including SRDs, TRDs, interface specifications, trade studies, and verification plans.
• Lead requirements decomposition, allocation, traceability, and burndown across subsystem teams.
• Support major lifecycle reviews including SRR, PDR, CDR, test readiness, and operational readiness reviews.
• Define system-level verification and validation strategies with integration and test teams.
• Provide technical leadership on interfaces, timing, throughput, resource utilization, high-speed data movement, and payload processing behavior.
• Communicate technical recommendations, risks, and tradeoffs to engineering and program leadership.
• Mentor engineers and help improve systems engineering practices, standards, and digital payload development processes.

Requirements

• Bachelor’s degree in Engineering, Physics, Computer Engineering, Electrical Engineering, or related technical field, or equivalent experience.
• 8+ years of relevant experience in systems engineering, digital payload development, FPGA or ASIC based systems, aerospace, space, or mission-critical systems.
• Demonstrated ability to independently define ambiguous technical problems, select appropriate methods, and drive resolution across teams.
• Proven experience owning payload or system-level technical budgets for performance, latency, throughput, power, timing, resources, margin, and risk.
• Deep experience with requirements development, decomposition, allocation, traceability, and verification closure.
• Strong understanding of full lifecycle systems engineering from concept definition through integration, verification, and operational readiness.
• Significant FPGA and ASIC architecture or implementation experience.
• Strong technical foundation in DSP, communication systems, high-speed digital interfaces, and payload data path architecture.
• Proficiency with VHDL, Verilog, SystemVerilog, or equivalent hardware description languages.
• Deep understanding of SERDES, transceivers, clocking architectures, synchronization, timing closure, high-speed link bring-up, and lab debugging.
• Ability to influence technical outcomes across multidisciplinary teams without direct authority.
• Strong communication skills for senior-level design reviews, risk discussions, and technical decision forums.
• Experience mentoring engineers and improving systems engineering practices, standards, and digital payload development processes.

Benefits

• Salary range: $180,500.00 - $285,000.00 annually (base pay range for specific work locations within San Jose / San Francisco Bay area and New York City metro: $224,500.00 - $336,500.00 annually).