Principal Digital Design Engineer / Chip Lead

Quick Facts

• Role: Digital Design Engineer / Chip Lead
• Focus: Chip architecture, RTL design, timing closure, synthesis, verification coordination, and tape-out ownership for high-speed interface PHY innovations

Description

As a Digital Design Engineer / Chip Lead, you are the technical anchor of a deliberately small, senior team bringing high-speed interface innovations from architecture to tape-out. The Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects, with a core emphasis on silicon-based validation of novel PHY solutions.

What You’ll Own

Chip Architecture & Integration

• Define top-level chip architecture
• Partition responsibilities across hard and soft IP blocks
• Own integration of hard macros alongside third-party soft IP

RTL Design

• Author, review, and maintain synthesizable RTL (SystemVerilog) for soft IP control blocks, CSR/register file, clocking control logic, and top-level integration

Timing Closure Leadership

• Develop and own chip-level timing constraints (SDC)
• Define clock domain crossing strategy
• Provide timing budgets per block to the Physical Design engineer

Synthesis

• Drive logic synthesis (DC / Genus)
• Guide optimization for PPA targets across all design blocks

Verification Coordination

• Partner with DV staff to apply assertion-based verification, coverage-driven verification, formal methods, and constrained-random techniques
• Ensure high quality verification of control logic, interfaces, and system behaviors

IP Management

• Define interfaces between PHY hard macro, third-party soft IP, and internally designed blocks
• Manage IP integration agreements and vendor coordination

Tape-Out Ownership

• Own and drive the tape-out checklist sign-off process
• Coordinate across Physical Design, Verification, and analog team members for clean foundry handoff

Design Documentation

• Author architecture specifications, block-level design specifications, and interface control documents

Follow-On Roadmap

• Capture design decisions, lessons learned, and architectural rationale to accelerate follow-on chip development

What You Bring

Required

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role
• Expert-level proficiency in SystemVerilog RTL design and coding best practices
• Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus)
• Proficiency with industry-standard RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug)
• Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent)
• Demonstrated experience integrating hard and soft IP blocks in a mixed-signal or PHY-adjacent chip environment
• Ability to work effectively as a technical lead on a small team; comfortable making decisions with incomplete information and owning outcomes
• Strong written communication skills; role produces specifications, not just code
• Experience partnering with design verification teams to define verification plans, review coverage metrics, and drive closure of functional and corner-cases prior to tape-out
• Expected to be proficient in leveraging AI for productivity

Preferred

• Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O structures)
• Familiarity with I2C management bus architecture, Eye Monitor control logic, or PRBS-based error counting implementations
• Experience with DFT strategy definition including scan insertion, ATPG planning, and boundary scan for high-speed I/O
• Familiarity with OTP/fuse-based trim and calibration architectures for PHY analog parameters
• Prior experience in a small team or startup-like environment where role boundaries are defined by need rather than org chart

Why This Role

• Full technical ownership of a chip from day one; no waiting for a senior engineer to hand you a subsystem
• Close collaboration with analog designers, including deep SerDes and clocking expertise; analog and digital work as collaborators
• Small and senior team; fast decisions and trusted judgment
• Join an active program with momentum; technical leadership directly shapes trajectory and scope going forward

Benefits

• Choice of medical, dental and vision plans
• Benefit programs to protect income if unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program and paid holidays
• Additional details available in the Benefits Guide posted on micron.com/careers/benefits