Hardware Test Engineer

Quick Facts

• Role: Hardware Test Engineer

• Experience: 5–7 years

• Location: Chicago, IL (Hybrid)

• Engagement: Long term • Contract / Full time

Description

The Hardware Test Engineer will take embedded and digital hardware designs from schematic through bring-up testing, executing functional and performance verification. The role emphasizes debugging PCIe Gen1 links, designing and validating low-voltage power trees, and supporting precision low-noise mixed-signal subsystems. You will collaborate with PCB layout, firmware, and system engineering teams and perform RCA during development, validation, and production.

Responsibilities

• Execute design validation, board bring-up, functional testing, and performance verification.
• Perform root cause analysis (RCA) and debug hardware issues across development, validation, and production phases.
• Support bring-up and validation using oscilloscopes, logic analyzers, and protocol analyzers with documented test results.
• Collaborate with PCB layout, firmware, and system engineering teams on design reviews, DFM/DFT feedback, and component selection (including lifecycle/obsolescence checks).

Requirements

• 5–7 years hands-on experience with digital and embedded hardware design, including concept/schematic to bring-up testing.
• Experience designing and debugging PCIe Gen1 (clock distribution, AC coupling, lane routing constraints, link training issues, eye/compliance debug).
• Experience with low-voltage DC power design (power tree/sequencing; buck converters and LDOs; power-integrity checks; low-power techniques such as power budgeting, sleep modes, and leakage reduction).
• Practical high-speed signal integrity knowledge (impedance-controlled stackups, termination, crosstalk, return-path management, and pre-/post-layout SI review).
• Experience with precision analog and low-noise mixed-signal design (ADC/DAC, sensor front ends, reference and op-amp design, analog/digital grounding and partitioning, noise budgeting).
• Proficiency in Cadence Allegro Design Entry HDL (Concept HDL) for schematic capture, including library/symbol management and clean BOM/netlist handoff to layout.
• Experience with serial/peripheral interfaces including SPI, I2C, UART, USB, and GPIO (level shifting, pull-up sizing, bus timing, and protocol-level debugging).
• Strong ability to document test results and collaborate across engineering teams.