Memory Design Interface Architect

Quick Facts

• Role: Memory Design Interface Architect (HBM IO)

Description

Own HBM IO blocks and the surrounding subsystems end-to-end, from specification through tape-out, bring-up, and post-silicon debug. Drive interface requirements across the HBM PHY, controller-to-PHY, die-to-die, clocking, training, electrical/power/error features, and test—including support for future interfaces. Lead performance-area-reliability trade-offs and coordinate cross-functional execution across packaging and advanced (2.5D/3D) assemblies.

Responsibilities

• Own HBM IO blocks/subsystems from architecture through circuit and RTL implementation, verification, tape-out, bring-up, and post-silicon debug
• Define requirements for HBM PHY, controller-to-PHY, die-to-die links, clocking, training, calibration, power management, error handling, and test (support future interface technologies)
• Manage trade-offs: bandwidth, latency, power, area, reliability, signal integrity, power integrity, yield, and manufacturability
• Design analog, mixed-signal, and digital interface functions within the high-speed memory subsystem
• Collaborate with package, interposer, physical design, signal integrity, power integrity, and thermal teams to close the interface across 2.5D and 3D assemblies
• Lead root-cause analysis for hard bugs across circuit, RTL, architecture, process, package, interposer, and system (pre- and post-silicon)
• Run one or more interface programs: set spec, plan, risks, and schedule; align architecture, design, layout, verification, validation, packaging, test, and product engineering
• Work with internal teams, IP providers, foundries, and partners to integrate high-speed memory and die-to-die interfaces
• Mentor engineers in architecture/build reviews and debug; tighten methods, guidelines, and reuse

Requirements

• 15+ years of experience in HBM, DDR, LPDDR, high-speed PHY, mixed-signal SoC, or ASIC design (or equivalent)
• Degree in Electrical Engineering, Computer Engineering, or related field (or equivalent experience)
• Experience taking complex interface IP/subsystems from architecture through silicon bring-up and post-silicon debug
• Deep experience in high-speed memory-interface architecture and design; HBM product families preferred
• Analog and mixed-signal circuit design and digital microarchitecture experience including RTL, clocking, training, calibration, power management, and error handling
• Front-end implementation/verification: synthesis, static timing, logic equivalence, and RTL debug
• Experience leading technical execution across disciplines and sites
• Working knowledge of DRAM operation, HBM and DDR, JEDEC, and memory subsystems

Benefits

• Lead end-to-end HBM interface architecture and delivery, including tape-out and post-silicon debug
• Broad cross-functional scope across circuit/RTL, verification, packaging/interposers, signal/power integrity, and thermal co-design
• Technical leadership and mentoring focused on improving interface design and debug methods