Unlock Full Resume Report
ATS Pass
Missing keywords
Tailored AI suggestions
Job match analysis
Interview-focused insights
New offer - be the first one to apply!
September 14, 2026
Principal Signal and Power Integrity Engineer
Senior • On-site
185,000 - 240,000 USD/yr
San Jose, CA
Apply now
Quick Facts
Principal Signal and Power Integrity Engineer (onsite)
Description
Execute SI planning, design, modeling, simulation, and lab validation with various system configurations for connectivity products used in Artificial Intelligence and Machine Learning applications.
Responsibilities
- Perform SI/PI planning and high-speed interconnect design work across multiple system configurations
- Conduct 2D and 3D electromagnetic (EM) modeling, simulation, and lab validation
- Model BGA and connector structures
- Run high-speed SERDES channel simulations and equalization
- Perform PI simulations using Ansys/Cadence toolsets
- Debug and analyze issues; lead root cause and correction action efforts
- Collaborate cross-functionally with the electrical design community to develop systems
Requirements
- Bachelor’s degree in Electrical Engineering (Master’s preferred)
- 8+ years experience supporting/developing complex SoC/silicon products for Server and Networking applications
- 8+ years hands-on high-speed SI/PI design, simulation, and measurement experience
- Proven track record defining hardware system constraints and high-speed technology roadmaps
- Cross-functional design mentality with the electrical design community
- Self-starting, professional, and hands-on work ethic able to execute intense research in a dynamic environment
- Proven track record solving problems independently (preferably as a tech lead)
- Entrepreneurial, open-minded behavior and can-do attitude
- Authorized to work in the US and start immediately
- Familiar with SI/PI design challenges for PCIe Gen5/6 and/or 224/448G Ethernet PCB and interconnects
- 2D/3D EM simulation experience with Cadence/Ansys/ADS tools
- EM modeling of BGA and connector structures
- High-speed SERDES channel simulation and equalization
- PI simulations with Ansys/Cadence toolsets
- Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes
- Working knowledge of PCB fabrication limits and trade-offs
- Familiar with PCI-SIG and IEEE802.3 (especially Electrical sections)
- Strong debugging, analysis, and problem-solving skills; experience leading root cause/correction action teams
- Ability to multi-task in a fast-paced environment
Benefits
- Base salary range: $185,000–$240,000 USD (Principal) or $237,500–$250,000 USD (Senior Principal), determined by experience and interview outcome
Similar jobs you might like

Expert IT Analyst (K/M)
ASTEK Polska
Senior
Technology
Warsaw, MZ, Poland · On-site
250K zł - 291K zł/yr
12 days ago

Technical Lead - BI
ASTEK Polska
Senior
Technology
Warsaw, Maz, Poland · Remote
$2621K - $2621K/yr
4 days ago

API Integration Engineer
ASTEK Polska
Senior
Technology
Warsaw, Maz, Poland · Remote
1872K zł - 1976K zł/yr
4 days ago

Analityk Biznesowo-Systemowy (AI & OCR)
ASTEK Polska
Mid
Technology
Warsaw, Maz, Poland · On-site
1664K zł - 1976K zł/yr
5 days ago

Ekspert/Ekspertka ds. Architektury Odporności IT/Cyberbezpieczeństwa (DORA)
ASTEK Polska
Senior
Technology
Warsaw, MZ, Poland · On-site
270K zł - 354K zł/yr
12 days ago

Senior Test Automation Engineer / Senior Test Automation Engineerka
ASTEK Polska
Senior
Technology
Warsaw, MZ, Poland · On-site
N/A
11 days ago

Senior Test Manager/QA Lead (K/M)
ASTEK Polska
Senior
Technology
Warsaw, MZ, Poland · On-site
1K zł - 1K zł/yr
9 days ago

PRODUCT OWNER – DATA & AI
ASTEK Polska
Senior
Technology
Warsaw, MZ, Poland · Remote
2080K zł - 2662K zł/yr
12 days ago

Senior QA Automation Engineer (K/M) - Java / API
ASTEK Polska
Senior
Technology
Warsaw, MZ, Poland · On-site
1K zł - 1K zł/yr
10 days ago

Agentic SDLC Senior Engineer (F/M)
ASTEK Polska
Senior
Technology
Warsaw, Poland · On-site
1K zł - 1K zł/yr
12 days ago
