Mempath Architect

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or equivalent practical experience.
• 15 years of industry experience in memory controller architecture, micro-architecture, or ASIC design.
• Experience in architecture, micro-architecture, and design of DRAM memory controllers.
• Experience in ASIC architecture performance analysis, performance tools, and simulator development at different abstraction levels, such as cycle-accurate, TLM, or functional.

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Deep domain knowledge in coherent interconnects, caches, fabrics, memory systems, and memory controllers.
• Understanding of hardware performance monitors, profiling, power management, and optimization.

Description

Shape the future of DRAM memory subsystem and controller architecture for consumer SoCs. Bring together the architectural responsibilities for memory subsystems and memory controllers to drive architectural alignment, performance optimization, and hardware-software co-design.

Collaborate with hardware designers, validation teams, and software architects to build and test technologies. Work on memory system innovation using developments in DDR, process-in-memory, and other emerging DRAM advancements.

Responsibilities

• Define and maintain the end-to-end architectural strategy across memory subsystems and memory controllers for consumer SoCs.
• Lead performance, power, and area trade-off analyses, feature design, clocking, and power-state management across memory IPs.
• Author comprehensive hardware architectural specifications, system-level design requirements, and programmer guides for next-generation memory controllers.
• Evaluate architectural choices by developing C models, executing workload simulations, and collaborating with verification and emulation teams.
• Serve as the primary technical contact for memory path latency, power optimization, and performance across cross-functional engineering teams.