Principal Engineer, RFIC

🏢 Summary: Senior RFIC Design Engineer role focused on developing next-generation low-power, low-voltage RF transceivers and mixed-signal circuits using advanced deep-submicron CMOS technologies. The position involves leading chip-level design verification, production support, and post-silicon validation while collaborating with digital and software teams. The role also includes research and implementation of advanced wireless techniques for highly integrated RFICs. 🗂️ Requirements: Bachelor’s with 20+ years, Master’s with 18+ years, or PhD with 15+ years in related field, Extensive hands-on experience in RF/Analog IC design in deep sub-micron CMOS, Experience designing LNA, Mixer, VGA, PA, VCO circuits, Ability to translate RF transceiver system requirements into circuit specifications, Experience with chip-level verification and production support, Technical leadership and mentoring experience, Post-silicon validation expertise, Proficiency with IC design CAD tools, Understanding of physical layout requirements and ability to perform critical layouts 📃 Skills: RFIC, CMOS, LNA, Mixer, VGA, PA, VCO, SerDes, DDR, ADC, DAC, Spectre, SpectreRF, Spice, Matlab, ADS 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.Samsung Semiconductor Inc. (SSI) is advancing the world's technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams. Advanced Circuit and Systems (ACAS) is looking for a highly skilled engineer that has strong background and hands-on experience on RFIC design. The candidate will be developing next-generation RF transceivers and mixed-signal circuits for What You'll Do Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS technologies. Lead efforts to perform chain and chip level design verification and production support tasks. Work closely with digital and software developers to develop an implementation that meets system requirements. Research in advanced wireless techniques for highly integrated RFICs What You Bring Bachelor's with 20+ years of experience or Master's with 18+ years of experiences or PhD with 15+ years of experience in a related field. Hands-on experience in designing various RF/Analog integrated circuits, such as LNA, Mixer, RF VGAs, PA, VCO, etc., in deep sub-micron CMOS technologies. Ability to comprehend RF transceiver system level requirements and translate into circuit level specifications. Excellent problem solving and analytical skills are essential. Technical leadership, mentoring, and post-silicon validation expertise are essential. Specialized knowledge in high-speed I/Os (SerDes, DDR) or data converters is a bonus. Strong knowledge on IC design CAD tools such as Spectre, SpectreRF, Spice, Matlab, and/or ADS. Thorough understanding of the physical layout requirement and ability to perform the critical layouts. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. #LI-VL1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$214,060—$341,940 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior mixed-signal/analog design role focused on high-speed memory I/O interfaces and advanced CMOS technologies. The position involves analog circuit design, simulations, layout guidance, verification, and silicon bring-up for technologies such as DDR, LPDDR, GDDR, and HBM. Candidates will work on PLL, SERDES, and high-speed data converter solutions supporting next-generation machine learning and data-centric applications. 🗂️ Requirements: BS/MS/PhD in Electrical Engineering or Computer Science, 5+ years in SoC architecture and analog mixed-signal circuit design, Experience with high-speed serial interfaces, Experience with DDR, LPDDR, GDDR, or HBM I/O interfaces, Expertise in high-speed circuit layout requirements, Knowledge of DLL, PLL, FFE, CTLE, DFE, ODT, DCC, and training/calibration, Experience with advanced CMOS technology nodes, Experience with high-frequency clock distribution design, Understanding of PPA trade-offs, Proficiency with EDA tools, Experience with silicon bring-up and automated measurements, Strong Tcl/Perl scripting skills, Ability to work onsite in San Jose 📃 Skills: DDR, LPDDR, GDDR, HBM, SERDES, PLL, DLL, FFE, CTLE, DFE, ODT, DCC, CMOS, Cadence, MATLAB, Simulink, Python, Tcl, Perl, EDA 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Memory IO Lab is part of the Memory Business Unit focused on memory interface technology solutions for DDR, LPDDR, GDDR, and related technologies. The team works closely with cross-disciplinary development teams to bring feature innovation to product roadmaps supporting machine learning applications, data analytics, and edge computing. Location: Daily onsite presence at the San Jose headquarters in alignment with the Flexible Work policy. What You'll Do - Hands-on analog circuit design including circuit implementation, simulations, and verification collaboration. - Work on mixed-signal designs including high-speed data converters, PLL, and SERDES. - Guide layout floor-planning at block and top level to optimize performance. - Supervise layout activities and provide guidelines to layout engineers. - Participate directly in layout drawing when necessary. - Own circuit and system specifications. - Simulate designs using advanced CAD tools. - Document designs and simulation results. What You Bring - BS with 10+ years, MS with 8+ years, or PhD with 5+ years of experience in Electrical Engineering or Computer Science. - 5+ years of experience with system-on-chip architecture, high-speed serial interfaces, and analog mixed-signal circuit design using advanced CMOS technology nodes. - Prior experience designing standard high-speed interfaces such as DDR, LPDDR, GDDR, or HBM I/O interfaces. - Expertise in layout requirements for high-speed circuits. - Knowledge of DLL, PLL, FFE, CTLE, DFE, output drivers, ODT, DCC, training/calibration, high-speed power design, and low-power design. - Experience working with device/process teams to define transistor specifications. - Ability to troubleshoot and analyze complex problems. - Experience in high-frequency clock distribution design, implementation, and analysis. - Deep understanding of performance, power, and area trade-offs. - Ability to use EDA tools such as Cadence, MATLAB/Simulink, and EM tools. - Experience with silicon bring-up and automated measurement scripting. - Strong scripting and automation skills using Tcl/Perl; Python knowledge is a plus. - Strong communication and interpersonal skills. - Ability to work in a fast-moving, dynamic environment. What We Offer - Competitive base pay range of $163,000—$253,000 USD. - Incentive opportunities based on individual and company performance. - Medical, dental, vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off plus holidays and sick leave. - Family support benefits including fertility care, adoption support, and medical travel support. - Emotional wellness resources including confidential therapy sessions. - Onsite café, gym, and virtual wellness classes. - Flexible work environment and wellbeing-focused benefits. Equal Opportunity Employment Policy Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process for candidates requiring support. Our Commitment to Innovation and Fairness AI tools may be used during recruitment as support tools only. Hiring decisions are made by recruiting teams and hiring managers. Applicant AI Use Policy Candidates are expected to rely on their own knowledge and skills during the application and interview process. AI tools may only be used for preparation, grammar, and research. Trade Secret Notice Applicants agree not to disclose confidential or proprietary information belonging to current or former employers.

🏢 Summary: Staff Engineer role focused on end-to-end design of high-performance, low-power SRAM circuits for advanced semiconductor nodes (2nm–5nm). The position involves driving PPA optimization, circuit simulation, physical verification, and methodology development for next-generation computing and AI platforms. It combines deep SRAM technical expertise with leadership and cross-functional collaboration. 🗂️ Requirements: Bachelor’s in Electrical Engineering + 10+ years experience or Master’s + 8+ years experience, Proven experience in SRAM or memory circuit design at advanced process nodes, Expert knowledge of SRAM architecture including bitcells, sense amplifiers, write drivers, control paths, Strong understanding of semiconductor device physics and advanced process technologies, Experience with timing analysis, power analysis, and DFM, Proficiency in circuit simulation and variation analysis, Experience with physical verification (DRC, LVS), Knowledge of scripting for design automation, Experience with silicon debug and root-cause analysis, Experience with advanced nodes (5nm, 3nm, or below) 📃 Skills: SRAM, HSPICE, Finesim, Spectre, Cadence, Virtuoso, DRC, LVS, Python, Perl, TCL, FinFET, GAA, SOI, DFM, PPA 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms. This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design. Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). Optimize SRAM designs for performance, power and area (PPA) and yield. Develop custom layouts and perform physical design verifications (e.g., DRC, LVS). Evaluate trade-offs between speed, power, and area to meet design targets. Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification. Work with product and test engineers to develop test plans and support silicon bring-up. Mentor Junior engineers, providing guidance on SRAM design techniques and best practices. Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance. Contribute to patents, technical papers, or industry conferences to advance SRAM technology. What You Bring Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes. Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.). Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths. Familiarity with timing analysis, power analysis, and design for manufacturability (DFM). Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc. Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks. Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams. Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond). Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling). Background in silicon debug and root-cause analysis. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$163,000—$253,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Lead research and architecture design for next-generation AI systems, focusing on rack-scale co-design of AI workloads, memory, interconnects, and high-performance RISC-V CPUs. The role drives system-level modeling, simulation, and micro-architecture innovation to eliminate memory and bandwidth bottlenecks in large-scale AI platforms. It combines deep technical leadership with hands-on architecture research and cross-functional collaboration. 🗂️ Requirements: Ph.D. in Computer Science, Electrical Engineering, or related field, 10+ years in system-level architecture research or large-scale computing platform design, Expertise in AI workload-focused system architecture design, Strong experience in performance modeling and event-driven simulation, Deep knowledge of RISC-V, ARM, or x86 CPU architectures, Experience designing out-of-order CPU micro-architectures, Proficiency in transaction-level modeling (TLM), Experience with large-scale design-space exploration and PPA analysis, Hands-on programming experience in Python and C++, Ability to lead technical research teams and define architecture roadmaps 📃 Skills: RISC-V, ARM, x86, TLM, Python, C++, PPA, Simulation, Modeling, Microarchitecture 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do Lead cutting‑edge research on next‑generation AI system architectures. The role is responsible for end‑to‑end co‑design of AI workloads, system‑level modeling, hardware platforms, and high‑performance processors that leverage Samsung's advanced memory technologies to eliminate capacity, bandwidth, and large‑scale communication bottlenecks. Location: Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy AI System Architecture Leadership Define system‑level architectures that solve memory‑capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems). Build and maintain analytical and event‑driven simulation frameworks for compute‑memory‑network performance at rack scale. Conduct design‑space exploration and quantitative trade‑off studies (performance, power, cost) to guide architecture decisions. Partner with SAIT HQ teams to align modeling insights with real‑world AI system implementations. RISC‑V CPU Architecture Leadership Architect high‑performance, out‑of‑order RISC‑V CPU cores that serve as host processors for AI computing systems. Drive IPC‑focused feature path‑finding; lead micro‑architecture research through performance‑model simulation and workload analysis. Produce detailed micro‑architecture specifications and guide cache/memory hierarchy design for optimal AI workload execution. Research & Innovation Management Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of high‑impact publications. Present architectural insights and strategic recommendations to senior leadership and external partners. What You Bring Education: Ph.D. in Computer Science, Electrical Engineering, or a related field. Experience: 10+years in system‑level architecture research or large‑scale computing platform design, with a strong focus on AI workloads. Technical Expertise: Performance modeling, event‑driven simulation, and quantitative analysis of compute‑memory‑interconnect systems. Deep knowledge of modern CPU/accelerator architectures (RISC‑V, ARM, x86) and heterogeneous integration. Proven ability to design rack‑scale AI system architectures that address memory, bandwidth, and interconnect constraints. Proficiency with transaction‑level modeling (TLM) and event‑driven simulation for compute‑memory‑network co‑design. Experience in large‑scale design‑space exploration and PPA (performance, power, area/cost) trade‑off analysis. Expertise in architecture and micro‑architecture design of out‑of‑order CPUs. Hands‑on experience with simulation tools and programming languages such as Python and C++. Communication Skills: Excellent written and verbal communication; proven ability to deliver technical presentations to senior stakeholders. Preferred Experience Proven track record of publishing high‑impact research papers. Experience influencing product roadmaps through architectural recommendations. Strong collaborative history with cross‑functional teams (hardware, software, memory technology). You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change #LI-SF1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$246,000—$430,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified. Trade Secret Notice By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Technical Marketing Senior Manager role focused on custom SoC/ASIC business development, customer engagement, and cross-functional technical sales support in the semiconductor industry. The position involves managing customer relationships, identifying new business opportunities, and aligning customer requirements with silicon platform solutions. The role requires strong semiconductor expertise, technical marketing experience, and collaboration with US and Korea-based teams. 🗂️ Requirements: Bachelor's degree in Engineering, Business, or related field, 10+ years of experience or Master's degree with 8+ years of experience, Technical sales or technical marketing experience, Program management or field applications engineering experience, Pre-sales and post-sales customer support experience, Strong understanding of semiconductor industry, Knowledge of SoC (System on Chip), Ability to translate customer requirements into technical solutions, Executive-level presentation and communication skills, Ability to work with cross-functional global teams 📃 Skills: ASIC, SoC, Semiconductor, Engineering, Marketing, Sales, Packaging, Silicon, VOC, Presentations 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. We are seeking a Technical Marketing Senior Manager to join our System LSI - Custom SoC Sales and Business Development Team in San Jose, CA. In this role, you will be responsible for identifying new opportunities for custom SoC (ASIC) business, conducting pre-shaping activities including technical requirements review and commercial discussions with potential customers, and building relationships with customers across the US market. This customer-facing role is highly cross-functional, where you will also manage day-to-day account management activities on both the technical and business sides with internal and external teams. We are seeking a high-energy professional with strong communication skills towards internal stakeholders and customers, as well as the ability to lead and develop new processes and ideas. The successful candidate will thrive in a fast-paced, dynamic environment and be able to develop strategic relationships with customer teams. What You'll Do - Support the design-in activities and business operations by working with cross-functional teams across Engineering, Sales and Marketing teams to secure customer engagements. - Act as local support interface for US customers for existing accounts and ongoing programs. - Engage in engineering and commercial discussions with customers. - Conduct market surveys and develop new customers and applications. - Act as local point of contact for engineering/commercial VOC collection and lead issue resolution internally. - Report ongoing and future projects to US and Korea executives. - Build relationships with internal stakeholder teams such as Marketing, Sales, Product Planning and development teams. - Work with customer teams to map requirements to S.LSI offerings, identify gaps, and drive internal development teams to deliver technical solutions. - Develop relationships with customer teams to understand technology needs, application requirements, and define silicon/platform solutions. What You Bring - Highly technical background with strong business acumen. - Ability to synthesize technical and business information into executive-level presentations. - Bachelor's Degree in Engineering, Business, or related discipline and 10+ years of experience, or Master's degree with 8+ years of experience. - Technical sales and/or marketing experience, management experience, technical/customer program management, or field applications engineering experience. - Experience with both pre-sales and post-sales customer support. - Good understanding of the semiconductor industry, especially SoC (System on Chip). - Understanding or experience with ASIC design and manufacturing flow, including advanced packaging, is a plus. - Ability to analyze customer problems and map solutions to Samsung LSI offerings. - Frequent collaboration with Korea-based teams. - Korean language proficiency is a plus. What We Offer - Competitive compensation with incentive opportunities. - Medical, Dental, Vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off, holidays, and sick leave. - Fertility care or adoption support, medical travel support, and virtual vet care. - Emotional wellness support including therapy sessions and wellness apps. - Onsite café and gym with virtual fitness classes. - Flexible work environment. Base Pay Range $176,000—$280,000 USD

🏢 Summary: Staff Engineer role focused on end-to-end SRAM circuit design for advanced semiconductor technologies, including development of high-performance, low-power memory arrays for AI, mobile, and computing platforms. The position involves circuit design, simulation, physical verification, methodology automation, silicon bring-up support, and mentoring engineers. Candidates are expected to have deep expertise in SRAM architecture, advanced process nodes, and semiconductor device physics. 🗂️ Requirements: Bachelor's degree in Electrical Engineering with 10+ years of experience or Master's degree with 8+ years of experience, Experience in SRAM or memory circuit design, Proven delivery of SRAM designs in advanced process nodes, Knowledge of semiconductor device physics, Expertise in SRAM architecture and control circuits, Experience with timing analysis and power analysis, Proficiency with circuit simulation and design tools, Knowledge of scripting for automation, Experience with advanced technology nodes such as 5nm or 3nm, Experience with low-power SRAM design techniques, Background in silicon debug and root-cause analysis 📃 Skills: SRAM, HSPICE, Finesim, Spectre, Cadence, Virtuoso, Python, Perl, TCL, FinFET, GAA, SOI, DRC, LVS, DFM 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms. This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design. - Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). - Optimize SRAM designs for performance, power and area (PPA) and yield. - Develop custom layouts and perform physical design verifications (e.g., DRC, LVS). - Evaluate trade-offs between speed, power, and area to meet design targets. - Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification. - Work with product and test engineers to develop test plans and support silicon bring-up. - Mentor junior engineers, providing guidance on SRAM design techniques and best practices. - Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance. - Contribute to patents, technical papers, or industry conferences to advance SRAM technology. What You Bring - Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. - Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes. - Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.). - Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths. - Familiarity with timing analysis, power analysis, and design for manufacturability (DFM). - Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc. - Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks. - Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams. - Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond). - Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling). - Background in silicon debug and root-cause analysis. What We Offer - Competitive base pay range: $163,000—$253,000 USD. - Incentive opportunities based on individual and company performance. - Medical, Dental, Vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off, holidays, and sick leave. - Family support benefits including fertility care, adoption support, medical travel support, and virtual vet care. - Emotional wellness support with on-demand apps and therapy sessions. - Onsite café, gym, and virtual fitness classes. - Flexible work environment. Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel. Our Commitment to Innovation and Fairness AI tools may be used to support recruitment efficiency, but all hiring decisions are made by human recruiters and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation and research, but not for generating submitted content or live interview responses. Trade Secret Notice By submitting an application, candidates agree not to disclose confidential or proprietary information belonging to current or former employers.

🏢 Summary: Senior Analog/Mixed-Signal IC Design Engineer responsible for developing high-speed memory I/O circuits for advanced DRAM and NAND interfaces. The role involves hands-on design, simulation, layout supervision, and silicon bring-up for high-speed data converters, PLLs, and SERDES in advanced CMOS nodes. You will own circuit specifications and optimize performance, power, and area for next-generation memory interfaces. 🗂️ Requirements: BS/MS/PhD in Electrical Engineering or Computer Science, 5+ years in SoC architecture and high-speed serial interface design, Experience with analog and mixed-signal circuit design in advanced CMOS nodes, Experience designing high-speed interfaces (DDR, LPDDR, GDDR, or HBM), Expertise in high-speed I/O layout requirements, Knowledge of DLL, PLL, FFE, CTLE, DFE, DCC, ODT, output drivers, Experience with high-frequency clock distribution design, Proficiency with EDA tools for simulation and verification, Experience with silicon bring-up and automated measurement, Strong scripting skills in Tcl or Perl 📃 Skills: CMOS, SoC, DDR, LPDDR, GDDR, HBM, SERDES, PLL, DLL, FFE, CTLE, DFE, DCC, ODT, Cadence, MATLAB, Simulink, Tcl, Perl, Python, EDA 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.Memory IO Lab is part of Samsung's Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO's vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung's paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps. Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy What You'll Do Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES. Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary. Ownership of circuit and system specifications. Simulate designs with state-of-the-art CAD tools. Document designs and simulation results. What You Bring BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes. Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface. Needs to be an expert in providing and understanding layout requirements of high speed circuits. Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design. Experience working closely with device/process team to define transistor specs The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Ability to troubleshoot and analyze complex problems. Excellent communication (written and verbal) and interpersonal skills Experience in high frequency clock distribution design, implementation, and analysis. Deep understanding of PPA (performance, power, and area) trade-offs. Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools Experience on silicon bring-up and automatic measurement using script Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus. Self-motivated problem-solver with an ability to work well in a team. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$163,000—$253,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior SoC Design Principal Engineer role focused on developing memory and storage silicon solutions for machine learning, data analytics, and edge computing applications. The position involves SoC architecture, RTL design, IP integration, ASIC flow execution, and collaboration with verification and physical design teams. The offer includes comprehensive benefits, flexible work environment, and high-impact R&D work in advanced DRAM and storage technologies. 🗂️ Requirements: Bachelor's degree in Electrical Engineering, Computer Science or related field with 20+ years of experience, or Master's with 18+ years, or PhD with 15+ years, Experience with ASIC design flow from design to tape out, Experience in ATE vector generation, testing, and silicon bring-up, Knowledge of commercial IPs including UCIe, CPU, Ethernet, and DDR interfaces, Experience in SoC synthesis, timing analysis, lint checks, and CDC checks, Experience interfacing with third-party service companies for DFT/PI/PD, Knowledge of AMBA bus fabric and ARM cores, Experience with RTL implementation and top-level SoC integration, Strong verbal and written communication skills 📃 Skills: ASIC, RTL, SoC, ARM, AMBA, DDR, UCIe, Ethernet, CDC, STA, DFT, Lint, Synthesis, ATE, Verilog 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. Principal Engineer, SOC Design What You'll Do The DRAM Development Lab (DDL) is part of Samsung's Memory Business Unit, focused on solving key problems of Cloud & Data center by developing new technology for memory and storage. The SOC team within DDL focuses on the development of silicon solutions and works closely with development teams to bring feature innovation to product roadmaps. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing. You'll focus on enhancement of memory and storage capability by developing prototype and production controllers. - Participate in architectural definitions and responsible for micro architecture of subsystem and/or chip level - Responsible for top integration, logic design and RTL implementation along with quality check (Assertion, Lint, CDC, and STA) - Review 3rd party IPs including ARM cores, DDR controller, and UCIe PHY - Responsible for integrating the third party IPs and subsystem at top level - Work closely with architects and verification engineers to ensure sound design at SoC level - Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis What You Bring - Bachelor's in Electrical, Computer Science or related with 20+ years of experience or Master's with 18+ years or PhD with 15+ years of industry experience preferred - Hands-on knowledge and experience in ASIC design flow from design to tape out - Experience and knowledge in ATE vector generation, testing and silicon bring up - Experience in commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces - Good understanding of PPA (performance, power, and area) trade-offs - Experience in SoC level synthesis, timing analysis, lint check, CDC checks - Experience interfacing with 3rd party service companies for DFT/PI/PD - Good knowledge and experience in AMBA bus fabric and ARM cores - Strong communication and collaboration skills What We Offer - Incentive opportunities based on individual and company performance - Medical, Dental, Vision, and 401k benefits - Charitable giving match and community involvement opportunities - 4+ weeks of paid time off plus holidays and sick leave - Fertility care or adoption stipend, medical travel support, and virtual vet care - On-demand wellness apps and confidential therapy sessions - Onsite café and gym plus virtual fitness classes - Flexible work environment Base Pay Range $219,000—$351,000 USD

🏢 Summary: Senior SoC Architect role responsible for translating customer requirements into a high-performance SoC architecture that meets aggressive power, performance, and area targets. The position leads top-level architecture definition, microarchitecture design, trade-off analysis, and validation for custom ASIC/SoC solutions. It involves cross-functional technical leadership from concept through implementation and verification. 🗂️ Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field, 8+ years experience in SoC Architecture or System Engineering, Experience in custom ASIC/SoC development, Deep knowledge of computer architecture and SoC design, Expertise in on-chip interconnects and high-speed interface protocols, Strong understanding of power management and low-power design, Experience with SoC clock, reset, and power domain architecture, Knowledge of RTL design and full SoC design flow, Experience with performance and power modeling, Proficiency in scripting languages 📃 Skills: SoC, ASIC, CPU, GPU, NPU, AMBA, AXI, CHI, PCIe, UALink, SystemC, C++, Python, Perl, RTL, DFx 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation. This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month. Reports to: Team leader/Head of Custom SoC Solutions Team What You'll Do Customer Requirement Definition and Architecture Design: Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI). Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN). Architecture Exploration and Validation: Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC). Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy. Technical Collaboration and Leadership: Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases. Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and What You Bring Bachelor's Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master's and 8+ years of experience. 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus) Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems). Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols. In-depth knowledge of Power Management and low-power design techniques. Experience with SoC-level Clock, Reset, and Power Domain architecture. Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification). Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues. Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients. Proficiency in scripting languages such as Python/Perl You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-VL1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$189,000—$301,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior RTL Engineer role focused on developing high-fidelity power macromodels for AI memory IP by translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. The position involves power feature extraction, model calibration, and validation against RTL, gate-level, and silicon data. The role requires onsite collaboration to enable scalable, system-level power simulation. 🗂️ Requirements: Bachelor’s degree with 20+ years of experience or Master’s degree with 18+ years of experience, Strong RTL design, synthesis and analysis experience, Proficiency in Verilog, SystemVerilog and SystemC, Solid understanding of dynamic and leakage power in CMOS and interconnects, Hands-on experience with logic synthesis and power analysis tools, Experience with power modeling and architectural power analysis, Ability to abstract RTL into analytical, LUT, FSM or ML-based models, Experience with trace-driven power modeling and model validation 📃 Skills: Verilog, SystemVerilog, SystemC, C, CMOS, VCS, VCFormal, DesignCompiler, PrimeTimePX, StarRC, PowerArtist, Verdi, McPAT, CACTI, Wattch, PlatformArchitect, RTL, FSM, LUT, ML 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid. Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations. Define power-relevant functional states (transaction/state-based abstraction). Support trace-driven power modeling, aligned with C/SystemC workload traces. Perform synthesis-assisted calibration using average and worst-case power anchors when available. Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available. Collaborate with software engineers on feature semantics, timing alignment, and model interfaces. Contribute to scalable IP-wise composition for full-system power simulation. What You Bring Bachelors degree 20+ years of experience or Masters degree 18+ years of experience. Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC). Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects. Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc. Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect. Familiarity with SystemC or transaction-level modeling. Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models. Knowledge of power macromodeling, power estimation flows, or architectural power analysis. Preferred Qualifications Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O. Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity. Exposure to low-power design and thermal management. Exposure to power macromodeling, power estimation flows, or architectural power analysis. What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$219,000—$351,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/