Staff Engineer, Mechanical Simulation

🏢 Summary: Thermal Engineer role focused on thermal analysis, simulation, and validation for advanced semiconductor and memory products. The position involves developing thermal models, performing steady-state and transient simulations, and collaborating with cross-functional teams to solve complex thermal challenges in enterprise electronics. Daily onsite work in San Jose is required. 🗂️ Requirements: Bachelor’s degree in Mechanical Engineering or related physical science with 10+ years of experience, Master’s degree in Mechanical Engineering or related physical science with 8+ years of experience preferred, PhD with 5+ years of experience preferred, Deep knowledge of thermal engineering, Expertise in FloTHERM, Experience with CFD tools, Strong background in heat transfer and fluid dynamics, Experience with thermal simulation and validation, Technical writing and verbal communication skills, Ability to execute independent research in a fast-paced onsite environment 📃 Skills: FloTHERM, CFD, Thermal, Simulation, HeatTransfer, FluidDynamics, SiP, AI 🏢 Description: We are currently seeking a Thermal Engineer. The position will be responsible for the thermal analysis and validation of thermal technologies for advanced semiconductor products. The ideal candidate will have a strong fundamental background in heat transfer, fluid dynamics, and thermal simulation with the implementation of thermal solutions in enterprise electronics. Location: Daily onsite presence at our San Jose, CA in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) What You'll Do - Develop reduced-order thermal models and rapid thermal analysis methods to guide architecture and development of memory products. - Execute high-fidelity and comprehensive thermal analysis and data validation at both the semiconductor component and system levels. - Provide rapid steady-state and transient simulation solutions for semiconductor products. - Collaborate with cross-functional internal teams and external partners to resolve complex thermal challenges. What You Bring - Bachelors degree in Mechanical Engineering (or related Physical Science) with 10+ years of experience or Masters degree Mechanical Engineering (or related Physical Science) with 8+ years of experience preferred or PhD Degree 5+ years of experience. - Proven self-discipline and professional maturity to execute independent research and meet rigorous milestones with a strong sense of accountability for both personal and collective goals in a fast-paced, on-site environment. - Deep knowledge and experience in Thermal Engineering. - Expertise in FloTHERM and familiarity with other CFD tools. - Excellent technical writing and verbal communication skills for collaboration, documentation, and presentations. Preferred Qualifications: - Fundamental understanding of IC chip/package architectures and thermal design constraints. - Working experience in SiP (System in Package) thermal analysis. - PhD degree in Thermal Engineering. - Minimum of 2 years of direct industry experience preferred. - Familiarity with Artificial Intelligence applications. - You're inclusive, adapting your style to the situation and diverse global norms of our people. - An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. - You're collaborative, building relationships, humbly offering support and openly welcoming approaches. - Innovative and creative, you proactively explore new ideas and adapt quickly to change. What We Offer - Incentive opportunities based on individual and company performance. - Medical, Dental, Vision, and 401k benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off, holidays, and sick leave. - Fertility care or adoption stipend, medical travel support, and virtual vet care. - On-demand wellness apps and confidential therapy sessions. - Onsite café and gym plus virtual fitness classes. - Flexible work environment. - Base pay range: $163,000—$253,000 USD.

🏢 Summary: Engineering role focused on developing and optimizing a trace-driven power and thermal simulation engine, integrating power macromodels, workload traces, and thermal solvers into a scalable system-level flow. The position involves building high-performance simulation frameworks and performing transient power and hotspot analysis. Daily onsite work in San Jose supporting advanced R&D in power and thermal modeling. 🗂️ Requirements: Bachelor’s degree with 5+ years experience or Master’s degree with 3+ years experience, Strong C++ software engineering experience, Experience building or extending simulation frameworks, Familiarity with discrete-event or time-stepped simulation architectures, Experience integrating IP-level power macromodels into system-level simulations, Ability to optimize performance and ensure scalability and reproducibility, Knowledge of numerical methods or reduced-order modeling 📃 Skills: C++, Simulation, Discrete-event, Time-stepped, Numerical-methods, Modeling, CFD, Thermal, Debugging, Optimization 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.The engineer develops and extends the trace‑driven power/thermal simulation engine, integrating power macromodels, workload traces, and thermal solvers into a coherent, scalable simulation flow. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) What You'll Do Implement and optimize trace‑driven power and thermal simulation engines. Integrate IP‑level power macromodels into system‑level simulation. Manage a time‑indexed simulation flow across power and thermal domains. Generate transient power maps and perform spatiotemporal hotspot analysis. Interface with reduced‑order thermal models and CFD‑calibrated solvers. Ensure simulation performance, scalability, and reproducibility. What You Bring Bachelors degree 5+ years of experience or Masters degree 3+ years of experience. Strong C++ software‑engineering background. Experience building or extending simulation frameworks. Familiarity with discrete‑event or time‑stepped simulation architectures. Solid software‑design, debugging, and performance‑optimization skills. Preferred Qualifications Experience with time‑indexed and event‑driven simulation. Knowledge of numerical methods or reduced‑order modeling. Exposure to data‑pipeline integration. #LI-VL1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$138,000—$206,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Staff Engineer role focused on memory systems architecture and in-field DRAM fault management for AI/ML data center deployments. The position involves analyzing telemetry data, developing RAS algorithms, improving ECC schemes, and collaborating with customers and industry groups on memory failure mitigation solutions. Daily onsite work in San Jose with research, proof-of-concept development, and standardization contributions. 🗂️ Requirements: Bachelor's degree with 10+ years of relevant experience or Master's with 8+ years or PhD with 5+ years, Experience in hardware fault management, reliability, or data center fleet management, Knowledge of platform memory subsystems and platform RAS features, Experience with ECC design, verification, and reverse engineering, Understanding of CPU-to-memory address mapping, Experience modifying memory controller registers, Linux kernel commit experience, Understanding of DRAM and HBM failure modes 📃 Skills: DRAM, HBM, ECC, RAS, Linux, Telemetry, hPPR, DIMM, SOC 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Samsung Semiconductor is hiring a Staff Engineer, Memory Systems Architecture. The conventional DRAM failure analysis was physical electrical FA and physical FA. In the era of data centers, field failure information is easier to track. The Fault Management team focuses on finding DRAM failure modes, abnormalities, and failure rate projections. You will be part of an incubation team working on in-field telemetry intended to transform the customer quality experience for Samsung memory products. Fault Management is focused on minimizing system downtime within AI/ML hardware deployments and workloads. The team analyzes trends and patterns from large-scale memory fleet telemetry to classify failures and perform virtual root-cause analysis. Telemetry analysis helps design solutions to proactively avoid system downtime. Research is conducted both internally and collaboratively with the industry, with opportunities to publish findings through whitepapers and conferences. What You'll Do - Based on knowledge of SOC controllers and memory operations including RAS features, identify and recommend solutions to mitigate field DRAM failure rates - Communicate improved ECC schemes to customers based on Samsung DRAM failure modes - Interface with customers to establish the value of enabling in-field fault management architecture - Contribute to the standardization of DRAM/HBM failure logging in the OCP - Propose and develop platform RAS algorithms for memory fault management such as page offlining and hPPR - Conduct proof-of-concept testing with known failure DIMMs in real servers and applications Location: Daily onsite presence at the San Jose headquarters in alignment with the Flexible Work Policy. What You Bring - Bachelor's degree with 10+ years of relevant industry experience, or Master's with 8+ years, or PhD with 5+ years in hardware fault management, reliability, data center fleet management, or related technical field - Knowledge of platform memory subsystems and platform RAS such as ECC, page offlining, hPPR, and hardware sparing - ECC design, verification, and reverse engineering experience - Understanding of address mapping between CPU and memory - Memory controller register modification experience - Linux kernel commit experience - Understanding of DRAM and HBM failure modes - Inclusive and collaborative working style - Curiosity, resilience, and data-driven problem solving - Innovative mindset and adaptability What We Offer - Competitive compensation with incentive opportunities - Medical, dental, vision, and 401(k) benefits - Charitable giving match and community involvement opportunities - 4+ weeks of paid time off plus holidays and sick leave - Fertility care or adoption support, medical travel support, and virtual vet care - Emotional wellness support with therapy sessions and wellness apps - Onsite café and gym plus virtual fitness classes - Flexible work environment Base Pay Range: $163,000—$253,000 USD Equal Opportunity Employment Policy Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process. Our Commitment to Innovation and Fairness AI tools may be used in recruitment as support tools, but all hiring decisions are made by human recruiters and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation, grammar, and research, but not for generating submitted content or live interview responses. Trade Secret Notice Applicants must not disclose confidential or proprietary information belonging to current or former employers.

🏢 Summary: Senior RTL Engineer role focused on developing high-fidelity power macromodels for AI memory IP by translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. The position involves power feature extraction, model calibration, and validation against RTL, gate-level, and silicon data. The role requires onsite collaboration to enable scalable, system-level power simulation. 🗂️ Requirements: Bachelor’s degree with 20+ years of experience or Master’s degree with 18+ years of experience, Strong RTL design, synthesis and analysis experience, Proficiency in Verilog, SystemVerilog and SystemC, Solid understanding of dynamic and leakage power in CMOS and interconnects, Hands-on experience with logic synthesis and power analysis tools, Experience with power modeling and architectural power analysis, Ability to abstract RTL into analytical, LUT, FSM or ML-based models, Experience with trace-driven power modeling and model validation 📃 Skills: Verilog, SystemVerilog, SystemC, C, CMOS, VCS, VCFormal, DesignCompiler, PrimeTimePX, StarRC, PowerArtist, Verdi, McPAT, CACTI, Wattch, PlatformArchitect, RTL, FSM, LUT, ML 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid. Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations. Define power-relevant functional states (transaction/state-based abstraction). Support trace-driven power modeling, aligned with C/SystemC workload traces. Perform synthesis-assisted calibration using average and worst-case power anchors when available. Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available. Collaborate with software engineers on feature semantics, timing alignment, and model interfaces. Contribute to scalable IP-wise composition for full-system power simulation. What You Bring Bachelors degree 20+ years of experience or Masters degree 18+ years of experience. Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC). Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects. Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc. Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect. Familiarity with SystemC or transaction-level modeling. Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models. Knowledge of power macromodeling, power estimation flows, or architectural power analysis. Preferred Qualifications Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O. Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity. Exposure to low-power design and thermal management. Exposure to power macromodeling, power estimation flows, or architectural power analysis. What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$219,000—$351,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior mixed-signal/analog design role focused on high-speed memory I/O interfaces and advanced CMOS technologies. The position involves analog circuit design, simulations, layout guidance, verification, and silicon bring-up for technologies such as DDR, LPDDR, GDDR, and HBM. Candidates will work on PLL, SERDES, and high-speed data converter solutions supporting next-generation machine learning and data-centric applications. 🗂️ Requirements: BS/MS/PhD in Electrical Engineering or Computer Science, 5+ years in SoC architecture and analog mixed-signal circuit design, Experience with high-speed serial interfaces, Experience with DDR, LPDDR, GDDR, or HBM I/O interfaces, Expertise in high-speed circuit layout requirements, Knowledge of DLL, PLL, FFE, CTLE, DFE, ODT, DCC, and training/calibration, Experience with advanced CMOS technology nodes, Experience with high-frequency clock distribution design, Understanding of PPA trade-offs, Proficiency with EDA tools, Experience with silicon bring-up and automated measurements, Strong Tcl/Perl scripting skills, Ability to work onsite in San Jose 📃 Skills: DDR, LPDDR, GDDR, HBM, SERDES, PLL, DLL, FFE, CTLE, DFE, ODT, DCC, CMOS, Cadence, MATLAB, Simulink, Python, Tcl, Perl, EDA 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Memory IO Lab is part of the Memory Business Unit focused on memory interface technology solutions for DDR, LPDDR, GDDR, and related technologies. The team works closely with cross-disciplinary development teams to bring feature innovation to product roadmaps supporting machine learning applications, data analytics, and edge computing. Location: Daily onsite presence at the San Jose headquarters in alignment with the Flexible Work policy. What You'll Do - Hands-on analog circuit design including circuit implementation, simulations, and verification collaboration. - Work on mixed-signal designs including high-speed data converters, PLL, and SERDES. - Guide layout floor-planning at block and top level to optimize performance. - Supervise layout activities and provide guidelines to layout engineers. - Participate directly in layout drawing when necessary. - Own circuit and system specifications. - Simulate designs using advanced CAD tools. - Document designs and simulation results. What You Bring - BS with 10+ years, MS with 8+ years, or PhD with 5+ years of experience in Electrical Engineering or Computer Science. - 5+ years of experience with system-on-chip architecture, high-speed serial interfaces, and analog mixed-signal circuit design using advanced CMOS technology nodes. - Prior experience designing standard high-speed interfaces such as DDR, LPDDR, GDDR, or HBM I/O interfaces. - Expertise in layout requirements for high-speed circuits. - Knowledge of DLL, PLL, FFE, CTLE, DFE, output drivers, ODT, DCC, training/calibration, high-speed power design, and low-power design. - Experience working with device/process teams to define transistor specifications. - Ability to troubleshoot and analyze complex problems. - Experience in high-frequency clock distribution design, implementation, and analysis. - Deep understanding of performance, power, and area trade-offs. - Ability to use EDA tools such as Cadence, MATLAB/Simulink, and EM tools. - Experience with silicon bring-up and automated measurement scripting. - Strong scripting and automation skills using Tcl/Perl; Python knowledge is a plus. - Strong communication and interpersonal skills. - Ability to work in a fast-moving, dynamic environment. What We Offer - Competitive base pay range of $163,000—$253,000 USD. - Incentive opportunities based on individual and company performance. - Medical, dental, vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off plus holidays and sick leave. - Family support benefits including fertility care, adoption support, and medical travel support. - Emotional wellness resources including confidential therapy sessions. - Onsite café, gym, and virtual wellness classes. - Flexible work environment and wellbeing-focused benefits. Equal Opportunity Employment Policy Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process for candidates requiring support. Our Commitment to Innovation and Fairness AI tools may be used during recruitment as support tools only. Hiring decisions are made by recruiting teams and hiring managers. Applicant AI Use Policy Candidates are expected to rely on their own knowledge and skills during the application and interview process. AI tools may only be used for preparation, grammar, and research. Trade Secret Notice Applicants agree not to disclose confidential or proprietary information belonging to current or former employers.

🏢 Summary: Staff Engineer role focused on end-to-end design of high-performance, low-power SRAM circuits for advanced semiconductor nodes (2nm–5nm). The position involves driving PPA optimization, circuit simulation, physical verification, and methodology development for next-generation computing and AI platforms. It combines deep SRAM technical expertise with leadership and cross-functional collaboration. 🗂️ Requirements: Bachelor’s in Electrical Engineering + 10+ years experience or Master’s + 8+ years experience, Proven experience in SRAM or memory circuit design at advanced process nodes, Expert knowledge of SRAM architecture including bitcells, sense amplifiers, write drivers, control paths, Strong understanding of semiconductor device physics and advanced process technologies, Experience with timing analysis, power analysis, and DFM, Proficiency in circuit simulation and variation analysis, Experience with physical verification (DRC, LVS), Knowledge of scripting for design automation, Experience with silicon debug and root-cause analysis, Experience with advanced nodes (5nm, 3nm, or below) 📃 Skills: SRAM, HSPICE, Finesim, Spectre, Cadence, Virtuoso, DRC, LVS, Python, Perl, TCL, FinFET, GAA, SOI, DFM, PPA 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms. This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design. Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). Optimize SRAM designs for performance, power and area (PPA) and yield. Develop custom layouts and perform physical design verifications (e.g., DRC, LVS). Evaluate trade-offs between speed, power, and area to meet design targets. Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification. Work with product and test engineers to develop test plans and support silicon bring-up. Mentor Junior engineers, providing guidance on SRAM design techniques and best practices. Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance. Contribute to patents, technical papers, or industry conferences to advance SRAM technology. What You Bring Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes. Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.). Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths. Familiarity with timing analysis, power analysis, and design for manufacturability (DFM). Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc. Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks. Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams. Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond). Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling). Background in silicon debug and root-cause analysis. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$163,000—$253,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: RTL Engineer role focused on developing advanced power macromodels for AI memory component IPs using RTL, SystemC, and C-based simulations. The position involves power feature extraction, model calibration and validation, and collaboration on scalable full-system power simulation. The role requires deep expertise in RTL design, synthesis, and power analysis tools for semiconductor and AI computing applications. 🗂️ Requirements: Bachelor’s degree with 10+ years of experience, Master’s degree with 8+ years, or PhD with 5+ years, Strong RTL design, synthesis, and analysis experience, Experience with Verilog, Experience with SystemVerilog, Experience with SystemC, Understanding of CMOS dynamic and leakage power mechanisms, Hands-on experience with synthesis and power analysis tools, Experience with power modeling frameworks and architectural power analysis, Ability to abstract RTL behavior into analytical and FSM-based models, Familiarity with transaction-level modeling 📃 Skills: Verilog, SystemVerilog, SystemC, CMOS, VCS, VCFormal, DesignCompiler, PrimeTimePX, StarRC, PowerArtist, Verdi, McPAT, CACTI, Wattch, Synopsys, RTL, FSM, LUT, AI, GPU 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. This role offers an opportunity to contribute to advanced AI computing and memory technologies through innovative power modeling and analysis. What You'll Do We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) Responsibilities: - Develop high-fidelity, advanced RTL-, SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and hybrid methods - Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations - Define power-relevant functional states using transaction/state-based abstraction - Support trace-driven power modeling aligned with C/SystemC workload traces - Perform synthesis-assisted calibration using average and worst-case power anchors when available - Validate macromodel accuracy against RTL/gate-level results and real-silicon data when available - Collaborate with software engineers on feature semantics, timing alignment, and model interfaces - Contribute to scalable IP-wise composition for full-system power simulation What You Bring - Bachelor’s degree with 10+ years of experience, Master’s degree with 8+ years, or PhD with 5+ years - Strong RTL design, synthesis, and analysis experience using Verilog/SystemVerilog/SystemC - Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects - Hands-on experience with logic synthesis and power analysis tools including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, and Verdi - Experience with academic and industry power modeling tools including McPAT, CACTI, Wattch, and Synopsys Platform Architect - Familiarity with SystemC or transaction-level modeling - Ability to abstract RTL behavior into analytical, table-based, FSM-based, and AI/ML models - Knowledge of power macromodeling, power estimation flows, and architectural power analysis Preferred Qualifications - Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O - Knowledge of cross-coupling capacitance, clock power modeling, and signal integrity - Exposure to low-power design and thermal management - Exposure to power macromodeling and architectural power analysis What We Offer - Competitive base pay range: $163,000—$253,000 USD - Incentive opportunities based on individual and company performance - Medical, dental, vision, and 401(k) benefits - 4+ weeks of paid time off plus holidays and sick leave - Fertility care, adoption support, medical travel support, and virtual vet care - On-demand wellness apps and confidential therapy sessions - Onsite café, gym, and virtual fitness classes - Flexible work environment and wellbeing-focused benefits

🏢 Summary: Staff Engineer role focused on memory systems architecture and in-field DRAM fault management for data center and AI/ML environments. The position involves analyzing large-scale telemetry data to identify failure modes, design RAS algorithms, and reduce system downtime through proactive memory fault mitigation. The role includes ECC design, failure analysis, and collaboration on industry standards for DRAM/HBM failure logging. 🗂️ Requirements: Bachelor’s degree with 10+ years / Master’s with 8+ years / PhD with 5+ years in hardware fault management or related field, Experience in hardware fault management, reliability, or data center fleet management, Knowledge of memory subsystems and platform RAS features, Experience with ECC design, verification, and reverse engineering, Understanding of CPU-to-memory address mapping, Experience modifying memory controller registers, Linux kernel commit experience, Understanding of DRAM and HBM failure modes 📃 Skills: DRAM, HBM, ECC, RAS, Linux, Telemetry, SoC, DIMM, OCP, AI, ML 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.Samsung Semiconductor is hiring now for a Staff Engineer, Memory Systems Architecture. The conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era of Data center, it is easier to track the field failure information. With this data set, Fault management team's role is finding DRAM failure mode, abnormality and failure rate projection. You will be part of an incubation team working on in-field telemetry intended to transform the Customer Quality Experience for Samsung memory products. Fault Management is the future of quality to minimize system downtime within AI/ML hardware deployments and workloads of the future. We analyze trends and patterns from enormous memory fleet telemetry to bucketize failures and perform virtual root-cause analysis. Telemetry analysis helps us design solutions to proactively avoid system downtime. We conduct research and develop both in-house and collaboratively in the industry with the opportunity to publish our findings through whitepapers and conferences. We are looking for innovative and passionate thinkers who can work in a start-up environment and are excited to shape the future of data centers around the world. Join us in our mission! What You'll Do Based on the knowledge of SOC controller and memory operation including RAS feature, find and recommends better solution to mitigate the field DRAM failure rate. Needs to communicate better ECC scheme to customers based on Samsung DRAM failure mode(DQ and burst) Interface with customers to establish the value add of enabling in-field fault management architecture Contribute to the standardization of DRAM/HBM failure logging in the OCP. Propose and develop platform RAS (Reliability Availability Serviceability) algorithms for memory fault management such as page offlining, hPPR and conduct POC with known failure DIMMs in the real server and application. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy. Job ID: 42886 What You Bring Bachelor's degree with 10+ years of relevant industry experience, or Master's with 8+ years or PhD with 5+ years hardware fault management, reliability, data center fleet management experience or related technical field preferred. (Must) Knowledge of platform memory subsystem, platform RAS (Reliability Availability Serviceability) such as ECC, page offlining, hPPR and hardware sparing. ECC design and verification and reverse engineering experience. Understanding on the address mapping between CPU and memory. Memory controller register modification. Linux kernel commit experience. DRAM and HBM failure mode understanding. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-MD1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$163,000—$253,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Staff Engineer role focused on end-to-end SRAM circuit design for advanced semiconductor technologies, including development of high-performance, low-power memory arrays for AI, mobile, and computing platforms. The position involves circuit design, simulation, physical verification, methodology automation, silicon bring-up support, and mentoring engineers. Candidates are expected to have deep expertise in SRAM architecture, advanced process nodes, and semiconductor device physics. 🗂️ Requirements: Bachelor's degree in Electrical Engineering with 10+ years of experience or Master's degree with 8+ years of experience, Experience in SRAM or memory circuit design, Proven delivery of SRAM designs in advanced process nodes, Knowledge of semiconductor device physics, Expertise in SRAM architecture and control circuits, Experience with timing analysis and power analysis, Proficiency with circuit simulation and design tools, Knowledge of scripting for automation, Experience with advanced technology nodes such as 5nm or 3nm, Experience with low-power SRAM design techniques, Background in silicon debug and root-cause analysis 📃 Skills: SRAM, HSPICE, Finesim, Spectre, Cadence, Virtuoso, Python, Perl, TCL, FinFET, GAA, SOI, DRC, LVS, DFM 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms. This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design. - Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). - Optimize SRAM designs for performance, power and area (PPA) and yield. - Develop custom layouts and perform physical design verifications (e.g., DRC, LVS). - Evaluate trade-offs between speed, power, and area to meet design targets. - Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification. - Work with product and test engineers to develop test plans and support silicon bring-up. - Mentor junior engineers, providing guidance on SRAM design techniques and best practices. - Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance. - Contribute to patents, technical papers, or industry conferences to advance SRAM technology. What You Bring - Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. - Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes. - Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.). - Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths. - Familiarity with timing analysis, power analysis, and design for manufacturability (DFM). - Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc. - Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks. - Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams. - Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond). - Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling). - Background in silicon debug and root-cause analysis. What We Offer - Competitive base pay range: $163,000—$253,000 USD. - Incentive opportunities based on individual and company performance. - Medical, Dental, Vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off, holidays, and sick leave. - Family support benefits including fertility care, adoption support, medical travel support, and virtual vet care. - Emotional wellness support with on-demand apps and therapy sessions. - Onsite café, gym, and virtual fitness classes. - Flexible work environment. Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel. Our Commitment to Innovation and Fairness AI tools may be used to support recruitment efficiency, but all hiring decisions are made by human recruiters and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation and research, but not for generating submitted content or live interview responses. Trade Secret Notice By submitting an application, candidates agree not to disclose confidential or proprietary information belonging to current or former employers.

🏢 Summary: Senior engineer role focused on leading and architecting functional test coverage and methodologies for NVMe enterprise SSDs, executing customer qualifications, and debugging system-level issues in enterprise server environments. The position involves hands-on testing, failure analysis, automation improvement, and close collaboration with internal and customer teams to ensure high-performance storage solutions meet enterprise standards. 🗂️ Requirements: BS in Computer Science or related field with 10+ years of system-level testing or enterprise server/storage development experience (or MS with 8+ years), Experience with enterprise servers and enterprise storage systems, Experience with at least one storage protocol: NVMe, PCIe, SAS, SATA, or Fibre Channel, Experience using protocol analyzers for system or device-level performance analysis, Proficiency with server operating systems and system debug tools, Experience with storage test tools, performance benchmarks, IO stress tools, and bug management tools, Scripting experience in Perl, Shell, or Python, Experience with SSD or HDD testing, Experience executing enterprise SSD qualifications in customer systems 📃 Skills: NVMe, PCIe, SAS, SATA, FibreChannel, LeCroy, SerialTek, Xgig, Perl, Shell, Python, SSD, HDD, Linux, Benchmarking, IO, Automation 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung's breakthrough V-NAND technology and enables our customers to power performance-oriented, demanding, enterprise-class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures. We are looking for a dynamic, self-motivated, experienced engineer to architect and lead functional test coverage and test methodologies for NVMe SSDs. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy. What You'll Do Manage Enterprise server infrastructure, execute Customer Qual tests and debug failures Execution of enterprise SSD qualifications in customer systems. Communicate with team lead to understand qualification processes and test plans. Report status of qualifications and manage customer expectations. Coordinate with internal team and customer test engineers to execute qual plans as per schedule. Teams will be both local and remote. Triage test failures and do a first level FA. Design and execute experiments to root cause defects and verify fixes in coordination with development teams. Provide feedback to functional test teams on issues seen in customer quals to better functional test coverage. Contribute in Triaging customer field issues and provide support for timely resolution of customer issues. Identify automation opportunities and help Automation team to continue to improve and add to the existing framework. What You Bring BS in Computer Science or related technical field with 10+ years of system level testing or development of enterprise servers and enterprise storage systems experience or MS with 8+ years preferred. Experience with at least storage protocol like NVMe/PCIe, SAS, SATA, Fibre Channel Familiar with one of protocol analyzers like LeCroy, SerialTek, or Xgig System or device level performance analysis Proficiency in server operating systems especially system debug tools such as system logs. Knowledge of enterprise storage/server system technologies. Expertise in storage test tools such as performance benchmarks, IO stress tools, protocol certifications, Test execution and bug management tools. Scripting experience such as in Perl, Shell or Python Experience with SSD or HDD testing NetApp/HPE/Dell/IBM System Experience You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-VL1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$163,000—$253,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/