CAD Automation and Machine Learning Engineer

Quick Facts

• Role: Build ML and large language model applications for circuit design automation and hardware IP reuse
• Focus: Integrate with CAD/circuit analysis workflows from transistor-level through signoff

Description

You will develop innovative machine learning (ML) and large language model (LLM) applications that help understand, explain, and interact with advanced circuit design software systems, integrated with internal compute infrastructure. The work includes optimizing and reusing delivery of hardware IP assets and supporting ML/LLM development processes by troubleshooting and resolving issues that can impact timelines. You’ll collaborate closely with multiple design teams and CAD experts to validate ML-based tools and evaluate EDA vendor and open-source solutions.

Responsibilities

• Develop ML and LLM applications for interaction with circuit design software systems and integration with compute infrastructure
• Identify opportunities to optimize, expedite, and reuse hardware IP asset delivery
• Support ML/LLM development workflows: understand input data, troubleshoot outputs, resolve software issues
• Collaborate with Custom Digital, Analog, Mixed-Signal, and other design teams to apply techniques that meet their ML/LLM needs and reduce duplicate work
• Validate ML-based applications with CAD experts; implement enhancements and evaluate EDA vendor packages and open-source solutions

Requirements

• BS in Computer Science or related field
• Knowledge of basic machine learning techniques
• Day-to-day experience with the UNIX shell environment
• Day-to-day experience with code revision control systems
• Knowledge of basic electrical engineering topics

Benefits

• Hands-on experience applying machine learning to circuit design automation and reuse of custom IP
• Broad exposure across silicon IP development stages and disciplines, including ML/LLM and transistor-level analysis and signoff workflows
• Highly visible role collaborating with dynamic teams and directly impacting state-of-the-art processors