Constrained Performance Modeling Engineer (Power & Thermal Platform Architecture)

Quick Facts

• Role: Constrained Performance Modeling Engineer (Power & Thermal – Platform Architecture)

• Focus: Build and drive constrained performance simulators for SoC performance/efficiency under power, thermal, and reliability constraints

Description

Design and develop constrained performance models and simulators to analyze Apple System-on-Chip (SoC) performance and operating efficiency while accounting for electrical, thermal, and reliability constraints and control systems. You will work closely with SoC, system, and software architects to influence architecture and implementation decisions for future products.

Responsibilities

• Build and maintain performance models under constrained power and thermal conditions; prepare new workloads for analysis

• Collaborate with architects and design teams to characterize workloads and identify optimization opportunities

• Partner with control engineers to model and optimize power, thermal, and reliability control systems

• Work with system design engineers to guide design decisions related to form factors

Requirements

• BS in Electrical Engineering, Computer Engineering, or a related engineering degree

• Experience in high-performance and low power microprocessor architecture and design techniques

• Experience coding in C, Python, or similar programming languages

Benefits

• Highly visible, cross-functional role driving development of performance simulators and influencing future product architecture