Principal Networking Architect, Ethernet Switch ASIC

Quick Facts

• Role: Principal Networking Architect (Ethernet Switch ASIC)

• Focus: Architecture from packet pipeline to MAC/PCS/SerDes and traffic management

• Coverage: Tapeout, silicon bring-up, and software interface

Description

You will define the end-to-end architecture for high-radix Ethernet switch ASICs, including the packet processing pipeline, buffering/traffic management, and the MAC/PCS/SerDes port subsystem. You will translate customer and market requirements into architecture specifications, performance models, and PPA trade-offs, then guide RTL, verification, physical design, and software teams through tapeout and silicon bring-up. You will also lead customer discussions and mentor architects to build an internal networking architecture practice.

Responsibilities

• Own the switch architecture end to end and drive throughput/latency/power/area targets in silicon

• Switch architecture: define top-level architecture for 12.8T–102.4T Ethernet switch ASICs (port mix, radix, pipeline count, die/chiplet partitioning)

• Packet processing: ingress/egress parsing; L2/L3 forwarding; tunneling (VXLAN, Geneve, MPLS, SRv6); ACLs; table lookups (TCAM, LPM, exact match, hashing, ECMP); define programmable pipeline features

• Traffic management: shared-buffer design; queuing/scheduling (strict priority, DWRR); shaping/policing; congestion management (ECN, PFC, lossless Ethernet, cut-through latency)

• AI/HPC fabrics: adaptive routing, packet spraying, RoCEv2 support, UEC capabilities, grained telemetry

• Port subsystem: specify MAC/PCS/FEC per IEEE 802.3; integrate 112G/224G SerDes; link training (IEEE 1588 PTP, SyncE); MACsec

• Memory/chip infrastructure: size on-chip SRAM/TCAM to define internal crossbar/fabric

• Specs/execution: write architecture and micro-architecture specs; guide RTL/DV/DFT/physical design/SDK teams; support emulation, FPGA prototyping, and post-silicon bring-up/debug

• Software interface: define programming model and SAI/SDK hooks; define telemetry interfaces; collaborate with SONiC/NOS teams

• Customers: translate customer requirements into specs; support proposals, estimates, and statements of work

• Leadership: mentor architects/designers and grow networking architecture practice

Requirements

• Production track record: architected Ethernet switch silicon that shipped

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or Computer Science

• 15+ years in networking ASIC/SoC development; 8+ years in architecture roles

• Architected at least one Ethernet switch ASIC (or switch/router NPU) that reached volume production; name the chip, scope, and result

• Deep knowledge of L2/L3 switching/routing, packet parsing/forwarding pipelines, and TCAM/LPM/hash-based lookups

• Hands-on experience with buffering, queuing, scheduling, and congestion control in high-bandwidth switches

• Knowledge of IEEE 802.3, IEEE 802.1, and RoCEv2

• Built performance models in C/C++/SystemC/Python and has enough SystemVerilog to review micro-architecture/RTL

• PPA trade-off experience on 7nm/5nm/3nm nodes with physical design teams

• Strong spec writing and ability to present architecture to customer engineering leaders and executives

Preferred Qualifications

• Architect on 51.2T+ switch generation, or with 224G SerDes designs

• AI/ML back-end fabric experience (adaptive routing, packet spraying, UEC-related specification)

• Programmable packet pipelines (P4 or equivalent)

• Multi-die/chiplet designs (UCIe) and familiarity with CPO or LPO

• Telemetry/timing: in-band telemetry, sFlow, high-precision timestamping

• Security engines: MACsec/IPsec

• SONiC/SAI/NOS integration

• Contributions to IEEE 802.3, UEC, OCP, or patents; experience in customer-facing/design-services roles