Principal Hardware Engineer, Networking

Quick Facts

• Role: Principal Hardware Engineer, Networking
• Focus: Technical leadership for complex network switch platforms for Azure AI infrastructure

Description

Lead multi-generation electrical and system architecture for custom network switch platforms supporting Azure AI infrastructure. Own requirements decomposition and technical authority across switch hardware subsystems, and drive execution from architecture and board design through integration, validation, manufacturing, and deployment. Translate ambiguous infrastructure needs into scalable platform solutions while managing technical risk and supplier execution.

Responsibilities

• Define and drive the multi-generation electrical and system architecture roadmap for custom network switch platforms (technology insertion, platform reuse, risk retirement, lifecycle strategy)
• Decompose platform-level requirements and make architectural tradeoffs across network, rack, performance, reliability, availability, serviceability, security, telemetry, manufacturing, cost, and schedule
• Provide technical authority for switch ASIC, control-plane CPU, BMC, CPLD/FPGA, clocking, reset, power delivery, high-speed Ethernet, retimers, optical modules, cable backplanes, telemetry, and platform-management interfaces
• Lead design reviews across schematic, PCB stack-up, signal integrity, power integrity, layout, BOM, component derating, DFT, DFM, DFR, and system integration; establish decision criteria and close cross-disciplinary issues
• Establish bring-up, electrical validation, margining, interoperability, stress, reliability, and production-test strategies with evidence-based exit criteria and scalable test coverage
• Lead resolution of complex board-, system-, rack-, manufacturing-, and field-level issues via cross-team debug, data-driven hypotheses, and prevention mechanisms
• Provide technical direction to ODM/OEM and technology partners; define deliverables, design-review criteria, quality expectations, and escalation paths while influencing supplier roadmaps
• Mentor senior engineers and raise engineering standards by creating reusable specifications, design guides, validation methods, reference architectures, and lessons learned

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 7+ years technical engineering experience; or Bachelor’s degree AND 8+ years technical engineering experience; or equivalent experience
• Ability to meet required security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years
• Experience leading architecture, requirements, design reviews, bring-up, validation, root-cause debug, and production readiness for complex hardware platforms

Preferred / Qualifications

• 10+ years designing and delivering board- or system-level hardware for networking, compute, storage, accelerator, or datacenter products across the hardware development lifecycle
• Experience developing high-speed serial and high-current power-delivery hardware across electrical, firmware, mechanical, thermal, SI/PI, validation, manufacturing, and system integration
• Technical leadership across internal organizations and external ODM/OEM, silicon, component, and manufacturing partners
• Proven ability to identify architectural and execution risks and drive decisions across performance, reliability, cost, schedule, and long-term platform value
• Experience architecting merchant-silicon Ethernet switch platforms for AI, cloud, hyperscale, or datacenter infrastructure
• Deep experience with switch ASIC, control-plane CPU, BMC, CPLD/FPGA, clocking, reset, power-delivery, telemetry, and hardware-management architectures
• Experience with 112G/224G PAM4, high-speed connectors, cable backplanes, retimers, pluggable optical modules, and end-to-end channel-budget tradeoffs
• Experience with SONiC hardware enablement, platform APIs, firmware interfaces, and switch-platform management
• Demonstrated ability to assess SI/PI analyses, PCB/package constraints, PDN behavior, power transients, thermal interactions, and laboratory correlation data
• Experience delivering hardware through EVT, DVT, PVT, production qualification, and high-volume manufacturing
• Experience defining supplier strategy and influencing technology roadmaps and ODM/OEM execution across multiple concurrent programs
• Strong technical communication, specification writing, executive-level decision framing, mentoring, and cross-organization influence

Benefits

• Typical U.S. base pay range: USD $142,800–$274,800 per year
• San Francisco Bay area & NYC metro base pay range: USD $188,000–$304,200 per year
• Eligible for benefits and other compensation (per corporate pay information)