Staff Hardware System Design Engineer

Qualcomm Technologies

San Diego, CA • 16m ago • On-site

Senior

On-site

145,600 - 218,400 USD/yr

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Potential salary for Staff Hardware System Design Engineer role

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$145,600 – $218,400/year

Quick Facts

  • Title: Staff Hardware System Design Engineer
  • Location: San Diego, CA (100% on-site)

Description

Own the end-to-end board design lifecycle for high-performance FPGA-based emulation platforms, including schematic capture, 26+ layer PCB stack-up, PCB layout, BOM management, power/signal-integrity simulation, and design verification testing. Drive system-level architecture with customers and software/firmware teams, including simulation and design-change recommendations for 10 Gbps+ SERDES and high-speed I/O. Lead lab bring-up, installation, debug, and cross-functional prototyping/support for multi-board systems.

Responsibilities

  • Own the board design lifecycle (schematics, PCB stack-up, PCB layout, BOM management, and design verification testing)
  • Drive system-level architecture with customer and software/firmware teams
  • Perform power and signal integrity simulations from model extraction through simulation, reporting, and recommended design changes for 10 Gbps+ signals
  • Lead/support FPGA board design (Xilinx and/or Altera), including DDR3/DDR4/DDR5 discrete memory subsystems
  • Direct lab technicians for system installation, bring-up, and debug; lead root-cause investigation of complex issues
  • Collaborate with mechanical, PCB layout, and manufacturing teams to optimize for signal integrity, DFM, and reliability
  • Author and maintain design documentation (HDDs, pinout tables, design review packages)
  • Serve as key/primary technical point of contact for system architecture decisions and trade-offs
  • Support factory production builds and NPI activities as needed

Requirements

  • Board design lifecycle experience: schematic capture, PCB stack-up (26+ layers), PCB layout, BOM management, and design verification testing
  • FPGA board design experience (Xilinx and/or Altera) and FPGA HDL coding experience
  • Experience designing for 10 Gbps+ SERDES and performing power/signal integrity simulations (model extraction to reporting and actionable recommendations)
  • Signal integrity and transmission line theory knowledge, plus circuit and layout guidelines for high-speed designs
  • Experience with DDR3/DDR4/DDR5 discrete component board designs
  • System architecture design experience; Staff-level requires defining architecture across multiple boards/platforms
  • Familiarity with I2C, JTAG, UART, SPI, SD Card, PCIe, and eMMC
  • Basic Linux/Unix experience
  • Familiarity with common EDA/tools and simulation workflows
  • Ability to work on-site in San Diego, CA; must be able to lift/move lab equipment and boards and support extended lab bring-up/debug

Benefits

  • Competitive annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Highly competitive benefits package

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