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August 20, 2026

Principal Post-Silicon Validation Engineer

Senior • On-site

1 - 999,999 USD/yr

San Jose, CA

About the team

The Post-Silicon Validation team brings up and validates the high-speed I/O and memory subsystems inside the DataScale platform, including PCIe, Ethernet, HBM, CXL, and UCIe interfaces. The team owns the path from first-silicon power-on through field deployment: characterization, stress testing, performance validation, and root-causing issues spanning silicon, board, and software. The team works directly with design, firmware, verification, and system engineering to keep bring-up on schedule and sign off on validation before product releases.

About the role

Seeking a Principal Engineer to own post-silicon bring-up, debug, and validation of high-speed I/O and memory subsystems within the DataScale platform. This role is central to delivering reliable, high-performance AI systems at scale. You will lead system-level debug across silicon, board, and software layers, driving issues to root cause from first silicon through field deployment. This is a hands-on role for an engineer with deep expertise in high-speed interfaces and hardware debug, who can operate in ambiguity and execute with high ownership.

Responsibilities

  • Own post-silicon bring-up and validation of high-speed I/O and memory subsystems, spanning characterization, functional validation, stress testing, and performance analysis.
  • Establish power-on readiness ahead of first silicon, including debug infrastructure, tooling, and contingency planning.
  • Lead system-level debug to root cause complex issues spanning silicon, board, and software layers.
  • Drive resolution with design, firmware, verification, and system teams to close issues and keep bring-up on schedule.
  • Partner with system and customer engineering teams on product validation, deployment, and RMA debug.
  • Own validation sign-off for product release against stability, performance, and field reliability targets.
  • Review SoC and board design and SI/PI analysis through a post-silicon debug and deployment lens.
  • Contribute to pre-silicon verification and emulation to improve bring-up efficiency and coverage.
  • Build scripts and tooling that automate validation, debug, and data analysis, and scale test coverage across systems.
  • Advance post-silicon validation methodology and debug infrastructure across programs.

Required Qualifications

  • M.S. in Electrical Engineering, Computer Science, or a related field.
  • 7+ years of experience in post-silicon validation or system bring-up.
  • Experience with two or more high-speed I/O or memory protocols such as PCIe, Ethernet, HBM, CXL, or UCIe.
  • Proven ability to lead cross-functional debug efforts to root cause and closure.
  • Strong analytical skills for test development and data analysis.
  • Proficiency in scripting such as Python and Bash.
  • Clear and effective communicator with a proactive, collaborative approach to problem-solving.

Preferred Qualifications

  • Deep understanding of high-speed SerDes training and adaptation.
  • Experience with mixed-signal I/O design and validation.
  • Hands-on lab experience with oscilloscopes, protocol analyzers, and BERTs.
  • Experience with optical interconnect.
  • Ability to read and debug C/C++.

Benefits Summary for US-Based, Full-Time Employment Positions

  • Competitive total rewards package, including base salary, equity, and benefits.
  • 95% premium coverage for employee medical insurance and 77% premium coverage for dependents.
  • Health Savings Account with employer contribution.
  • Dental, vision, short- and long-term disability, basic life, voluntary life, and AD&D insurance plans.
  • Flexible Spending Account options for health care, limited purpose, and dependent care.
  • Well-being benefits for employees and dependents, including Headspace, Gympass+ membership, One Medical membership, counseling services, and an Employee Assistance Program.

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