Staff Engineer, RTL

🏢 Summary: Senior RTL Engineer role focused on developing high-fidelity power macromodels for AI memory IP by translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. The position involves power feature extraction, model calibration, and validation against RTL, gate-level, and silicon data. The role requires onsite collaboration to enable scalable, system-level power simulation. 🗂️ Requirements: Bachelor’s degree with 20+ years of experience or Master’s degree with 18+ years of experience, Strong RTL design, synthesis and analysis experience, Proficiency in Verilog, SystemVerilog and SystemC, Solid understanding of dynamic and leakage power in CMOS and interconnects, Hands-on experience with logic synthesis and power analysis tools, Experience with power modeling and architectural power analysis, Ability to abstract RTL into analytical, LUT, FSM or ML-based models, Experience with trace-driven power modeling and model validation 📃 Skills: Verilog, SystemVerilog, SystemC, C, CMOS, VCS, VCFormal, DesignCompiler, PrimeTimePX, StarRC, PowerArtist, Verdi, McPAT, CACTI, Wattch, PlatformArchitect, RTL, FSM, LUT, ML 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do We are seeking an RTL engineer to develop high-fidelity, advanced IP-level power macromodels for AI computing memory component IPs. The role focuses on translating RTL/SystemC/C behavior into time-indexed, input-dependent power models. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) Develop high-fidelity, advanced RTL- SystemC-, and C-based power macromodels for AI memory component IPs using analytical modeling, LUT, FSM, NN, and their hybrid. Extract activity-, value-, and state-dependent power features from C/SystemC/RTL simulations. Define power-relevant functional states (transaction/state-based abstraction). Support trace-driven power modeling, aligned with C/SystemC workload traces. Perform synthesis-assisted calibration using average and worst-case power anchors when available. Validate macromodel accuracy against reference RTL/gate-level results and real-silicon data when available. Collaborate with software engineers on feature semantics, timing alignment, and model interfaces. Contribute to scalable IP-wise composition for full-system power simulation. What You Bring Bachelors degree 20+ years of experience or Masters degree 18+ years of experience. Strong RTL design, synthesis and analysis experience (Verilog/SystemVerilog/SystemC). Solid understanding of dynamic and leakage power mechanisms in CMOS and interconnects. Hands-on experience with logic synthesis and power analysis tools, including VCS, VC Formal, Design Compiler, PrimeTime-PX, StarRC, PowerArtist, Verdi, etc. Hands-on experience with power modeling in academia, including McPAT, CACTI, Wattch, etc. and industry tools such as Synopsys Platform Architect. Familiarity with SystemC or transaction-level modeling. Ability to abstract RTL behavior into compact analytical, table-based, FSM-based, and AL/ML models. Knowledge of power macromodeling, power estimation flows, or architectural power analysis. Preferred Qualifications Experience with GPU, computer architecture, AI memory, memory controllers, PHYs, or high-speed I/O. Knowledge of cross-coupling capacitance, clock power modeling, and power and signal integrity. Exposure to low-power design and thermal management. Exposure to power macromodeling, power estimation flows, or architectural power analysis. What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$219,000—$351,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Engineering role focused on developing and optimizing a trace-driven power and thermal simulation engine, integrating power macromodels, workload traces, and thermal solvers into a scalable system-level flow. The position involves building high-performance simulation frameworks and performing transient power and hotspot analysis. Daily onsite work in San Jose supporting advanced R&D in power and thermal modeling. 🗂️ Requirements: Bachelor’s degree with 5+ years experience or Master’s degree with 3+ years experience, Strong C++ software engineering experience, Experience building or extending simulation frameworks, Familiarity with discrete-event or time-stepped simulation architectures, Experience integrating IP-level power macromodels into system-level simulations, Ability to optimize performance and ensure scalability and reproducibility, Knowledge of numerical methods or reduced-order modeling 📃 Skills: C++, Simulation, Discrete-event, Time-stepped, Numerical-methods, Modeling, CFD, Thermal, Debugging, Optimization 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.The engineer develops and extends the trace‑driven power/thermal simulation engine, integrating power macromodels, workload traces, and thermal solvers into a coherent, scalable simulation flow. Location: Daily onsite presence at our San Jose, CA office in alignment with our Flexible Work policy Reports to: SVP, R&D (Power & Thermal Lab) What You'll Do Implement and optimize trace‑driven power and thermal simulation engines. Integrate IP‑level power macromodels into system‑level simulation. Manage a time‑indexed simulation flow across power and thermal domains. Generate transient power maps and perform spatiotemporal hotspot analysis. Interface with reduced‑order thermal models and CFD‑calibrated solvers. Ensure simulation performance, scalability, and reproducibility. What You Bring Bachelors degree 5+ years of experience or Masters degree 3+ years of experience. Strong C++ software‑engineering background. Experience building or extending simulation frameworks. Familiarity with discrete‑event or time‑stepped simulation architectures. Solid software‑design, debugging, and performance‑optimization skills. Preferred Qualifications Experience with time‑indexed and event‑driven simulation. Knowledge of numerical methods or reduced‑order modeling. Exposure to data‑pipeline integration. #LI-VL1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$138,000—$206,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior SoC Architect role responsible for translating customer requirements into a high-performance SoC architecture that meets aggressive power, performance, and area targets. The position leads top-level architecture definition, microarchitecture design, trade-off analysis, and validation for custom ASIC/SoC solutions. It involves cross-functional technical leadership from concept through implementation and verification. 🗂️ Requirements: Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field, 8+ years experience in SoC Architecture or System Engineering, Experience in custom ASIC/SoC development, Deep knowledge of computer architecture and SoC design, Expertise in on-chip interconnects and high-speed interface protocols, Strong understanding of power management and low-power design, Experience with SoC clock, reset, and power domain architecture, Knowledge of RTL design and full SoC design flow, Experience with performance and power modeling, Proficiency in scripting languages 📃 Skills: SoC, ASIC, CPU, GPU, NPU, AMBA, AXI, CHI, PCIe, UALink, SystemC, C++, Python, Perl, RTL, DFx 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.The SoC Architect will serve as a key technical leader, translating client requirements into an optimal SoC blueprint that achieves aggressive PPA (Power, Performance, Area) targets and driving its successful implementation. This role will be a critical leader who provides the technical blueprint that ultimately realizes our clients' business objectives and should have a deep understanding of the complexities of custom SoC development and the ability to leverage broad system knowledge to create innovative solutions. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy with an average of 20% travel per month. Reports to: Team leader/Head of Custom SoC Solutions Team What You'll Do Customer Requirement Definition and Architecture Design: Analyze and define the functional, performance, and power requirements based on the client's end product and application (e.g., mobile, edge device, data center or physical AI). Conceive and specify the Top-Level SoC Architecture and Microarchitecture, including CPU/GPU/NPU cores, memory subsystem, Interconnect (Coherent/Non-Coherent Fabric), and high-speed I/O interfaces (e.g., PCIe, UALink or ESUN). Architecture Exploration and Validation: Evaluate various architectural trade-offs and validate architectural decisions using performance and power modeling (C/C++, SystemC). Provide technical guidance on IP selection, integration, and system optimization, and define the Design for Debug/Test/Excellence (DFx) strategy. Technical Collaboration and Leadership: Collaborate closely with cross-functional teams (HW Design, Verification, Physical Design, Software) to ensure architectural specifications are accurately translated into the design and implementation phases. Identify and resolve technical risks throughout the project lifecycle, and lead technical communication with clients and What You Bring Bachelor's Degree in Electrical Engineering, Computer Science, or related discipline and 10+ years of experience, or Master's and 8+ years of experience. 5+ years experience in SoC Architecture or System Engineering (experience in custom ASIC/SoC projects is a plus) Deep understanding of Computer Architecture and SoC Design (including CPU, GPU, Accelerators, Caches, and Memory Systems). Expert knowledge and design experience with on-chip interconnects (e.g., AMBA AXI/CHI) and High-Speed Interface protocols. In-depth knowledge of Power Management and low-power design techniques. Experience with SoC-level Clock, Reset, and Power Domain architecture. Comprehensive understanding of the overall RTL design and SoC design flow (Implementation & Verification). Excellent problem-solving skills to independently identify, analyze, and resolve complex technical issues. Ability to communicate and negotiate effectively with diverse stakeholders, including hardware and software engineering teams, managements, and clients. Proficiency in scripting languages such as Python/Perl You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-VL1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$189,000—$301,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior Engineer role focused on developing and optimizing RTL IP for memory-centric computing systems supporting advanced AI/ML workloads. The position involves hardware-software co-design, microarchitecture development, SOC integration, and performance optimization for next-generation AI systems. 🗂️ Requirements: Bachelor's degree with 10+ years of experience, Master's with 8+ years, or PhD with 5+ years, Strong background in microarchitecture and computer architecture, 5+ years of RTL front-end design methodology experience, Experience developing complex control and datapath IPs, Experience with Memory Controller, NOC, and Interconnect IP design, Experience with memory-centric computing IP and SOC integration, Experience with AI/ML workloads, Strong analytical and problem-solving skills, Excellent communication and interpersonal skills, Ability to work independently and collaboratively 📃 Skills: Verilog, SystemVerilog, HLS, RTL, Microarchitecture, SoC, NOC, Interconnect, AI, ML 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. We are looking for a Senior Engineer, RTL Memory Centric Computing. This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design. What You'll Do - Develop IP for memory centric computing systems using Verilog, System Verilog and HLS - Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression - Collaborate with Verification engineers to design and develop test plans - Make design decisions out of a large design trade-off space across performance, power, thermal, and cost - Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation - Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies - Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget - Complete other responsibilities as assigned What You Bring - Bachelor's with 10+ years, or Master's with 8+ years, or PhD's with 5+ years of industry experience - Strong background in microarchitecture and computer architecture - 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs - Experience in designing Memory Controller, NOC, Interconnect IP - Experience in Memory Centric computing IP and SOC integration - Experience in AI/ML workloads - Strong analytical and problem-solving skills - Excellent communication and interpersonal skills - Ability to work independently and as part of a team - You're inclusive, adapting your style to the situation and diverse global norms of our people - An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding - You're collaborative, building relationships, humbly offering support and openly welcoming approaches - Innovative and creative, you proactively explore new ideas and adapt quickly to change What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. - Give Back with a charitable giving match and frequent opportunities to get involved in supporting the community - Enjoy Time Away with 4+ weeks of paid time off a year, plus holidays and sick leave - Care for Family including fertility care or adoption support, medical travel support, and virtual vet care - Prioritize Emotional Wellness with on-demand apps and free confidential therapy sessions - Stay Fit with onsite café and gym, plus virtual classes - Embrace Flexibility through a flexible work environment Base Pay Range $163,000—$253,000 USD

🏢 Summary: Lead research and architecture design for next-generation AI systems, focusing on rack-scale co-design of AI workloads, memory, interconnects, and high-performance RISC-V CPUs. The role drives system-level modeling, simulation, and micro-architecture innovation to eliminate memory and bandwidth bottlenecks in large-scale AI platforms. It combines deep technical leadership with hands-on architecture research and cross-functional collaboration. 🗂️ Requirements: Ph.D. in Computer Science, Electrical Engineering, or related field, 10+ years in system-level architecture research or large-scale computing platform design, Expertise in AI workload-focused system architecture design, Strong experience in performance modeling and event-driven simulation, Deep knowledge of RISC-V, ARM, or x86 CPU architectures, Experience designing out-of-order CPU micro-architectures, Proficiency in transaction-level modeling (TLM), Experience with large-scale design-space exploration and PPA analysis, Hands-on programming experience in Python and C++, Ability to lead technical research teams and define architecture roadmaps 📃 Skills: RISC-V, ARM, x86, TLM, Python, C++, PPA, Simulation, Modeling, Microarchitecture 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do Lead cutting‑edge research on next‑generation AI system architectures. The role is responsible for end‑to‑end co‑design of AI workloads, system‑level modeling, hardware platforms, and high‑performance processors that leverage Samsung's advanced memory technologies to eliminate capacity, bandwidth, and large‑scale communication bottlenecks. Location: Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy AI System Architecture Leadership Define system‑level architectures that solve memory‑capacity, bandwidth, and interconnect challenges for large AI workloads (e.g., large language models, recommendation systems). Build and maintain analytical and event‑driven simulation frameworks for compute‑memory‑network performance at rack scale. Conduct design‑space exploration and quantitative trade‑off studies (performance, power, cost) to guide architecture decisions. Partner with SAIT HQ teams to align modeling insights with real‑world AI system implementations. RISC‑V CPU Architecture Leadership Architect high‑performance, out‑of‑order RISC‑V CPU cores that serve as host processors for AI computing systems. Drive IPC‑focused feature path‑finding; lead micro‑architecture research through performance‑model simulation and workload analysis. Produce detailed micro‑architecture specifications and guide cache/memory hierarchy design for optimal AI workload execution. Research & Innovation Management Lead a multidisciplinary research team, set technical roadmaps, and ensure delivery of high‑impact publications. Present architectural insights and strategic recommendations to senior leadership and external partners. What You Bring Education: Ph.D. in Computer Science, Electrical Engineering, or a related field. Experience: 10+years in system‑level architecture research or large‑scale computing platform design, with a strong focus on AI workloads. Technical Expertise: Performance modeling, event‑driven simulation, and quantitative analysis of compute‑memory‑interconnect systems. Deep knowledge of modern CPU/accelerator architectures (RISC‑V, ARM, x86) and heterogeneous integration. Proven ability to design rack‑scale AI system architectures that address memory, bandwidth, and interconnect constraints. Proficiency with transaction‑level modeling (TLM) and event‑driven simulation for compute‑memory‑network co‑design. Experience in large‑scale design‑space exploration and PPA (performance, power, area/cost) trade‑off analysis. Expertise in architecture and micro‑architecture design of out‑of‑order CPUs. Hands‑on experience with simulation tools and programming languages such as Python and C++. Communication Skills: Excellent written and verbal communication; proven ability to deliver technical presentations to senior stakeholders. Preferred Experience Proven track record of publishing high‑impact research papers. Experience influencing product roadmaps through architectural recommendations. Strong collaborative history with cross‑functional teams (hardware, software, memory technology). You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change #LI-SF1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$246,000—$430,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Our Commitment to Innovation and Fairness At Samsung Semiconductor, we use Artificial Intelligence (AI) tools in the recruitment process to enhance efficiency. However, AI is used as a support tool, not a final decision-maker. All hiring decisions are made by our human recruiting team and hiring managers to ensure every candidate is evaluated fairly and holistically. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified. Trade Secret Notice By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Senior Engineer role focused on RTL development for memory-centric computing systems within an AI research lab, driving hardware–software co-design for next-generation AI/ML platforms. The position involves designing and optimizing complex IP blocks for performance, power, and area, supporting scalable high-performance AI systems. The role requires deep expertise in microarchitecture, memory subsystems, and SoC integration. 🗂️ Requirements: Bachelor’s with 15+ years, or Master’s with 13+ years, or PhD with 10+ years of industry experience, Strong background in microarchitecture and computer architecture, 5+ years of experience in RTL front-end design for complex control and datapath IP, Experience designing Memory Controller, NOC, or Interconnect IP, Experience with memory-centric computing IP and SoC integration, Experience with AI/ML workloads, Ability to optimize designs for performance, power, and area, Experience with hardware verification, debugging, and validation 📃 Skills: Verilog, SystemVerilog, HLS, RTL, Microarchitecture, ComputerArchitecture, MemoryController, NoC, Interconnect, SoC, AI, ML 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing! We are looking for a Senior Engineer, RTL Memory Centric Computing. This role is being offered under the AGICL lab as a part of DSRA. We are a research-driven systems lab working at the intersection of large language models, accelerator hardware, and high-performance software stacks. Our mission is to design, prototype, and optimize next-generation AI systems through tight hardware–software co-design. Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy. What You'll Do Develop IP for memory centric computing systems using Verilog, System Verilog and HLS Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression. Collaborate with Verification engineers to design and develop test plans Make design decisions out of a large design trade-off space across performance, power, thermal, and cost. Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation. Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to the development of new technologies. Communicate effectively with stakeholders, including users, partners, and management, to ensure that the systems are delivered on time and within budget Complete other responsibilities as assigned. What You Bring Bachelor's with 15+ years, or Master's with 13+ years, or PhD's with 10+ years of industry experience. Strong background in microarchitecture and computer architecture 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs Experience in designing Memory Controller, NOC, Interconnect IP Experience in Memory Centric computing IP and SOC integration Experience in AI/ML workloads. Strong analytical and problem-solving skills Excellent communication and interpersonal skills Ability to work independently and as part of a team You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change #LI-VL1 What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$189,000—$301,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Staff Engineer role focused on mechanical and thermal simulation for next-generation semiconductor packaging and memory devices, including modeling, reliability analysis, and workflow automation. The position involves cross-functional collaboration, validation testing, and development of advanced packaging solutions using industry-standard simulation tools. Daily onsite work in San Jose with some domestic and international travel is required. 🗂️ Requirements: Ph.D. in Mechanical Engineering, Materials Science, Physics, or related field, 3+ years of modeling and simulation experience in semiconductor or high-tech industry, Expertise with ANSYS, Abaqus, HyperMesh, Proficiency with Flotherm and Icepak, Experience with static and dynamic linear and nonlinear simulations, Knowledge of advanced semiconductor packaging and interconnect structures, Experience with reliability modeling techniques, Ability to develop automation scripts in Python, MATLAB, or ANSYS APDL, Technical writing and documentation skills, Ability to work with cross-functional global teams 📃 Skills: ANSYS, Abaqus, HyperMesh, Flotherm, Icepak, Python, MATLAB, APDL, Simulation, Modeling, Thermal, Mechanical, Semiconductor, Packaging, Reliability 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. Join Samsung Semiconductor to guide the development and design evaluation of next‑generation semiconductor packages and memory devices. In this role as a Staff Engineer for Mechanical Simulation, you will partner with cross‑functional, multicultural teams to advance innovative packaging solutions, automate simulation workflows, and bridge the gap between numerical predictions and experimental validation. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy with 10-20% of domestic and international travel. Reports to: Principal Engineer What You'll Do - Perform advanced numerical modeling and simulation to evaluate and improve the performance and reliability of cutting‑edge semiconductor packages and memory devices. - Provide mechanical and thermal design support throughout package‑ and system‑development stages—from concept and detailed modeling to qualification and reliability testing. - Apply hands‑on expertise in mechanical and thermal modeling of micro‑electronic components, including interconnects, solder joints, BGAs, and advanced‑packaging architectures. - Develop and maintain scripts for process automation (Python, MATLAB, or ANSYS APDL) to streamline pre‑processing, simulation, and post‑processing workflows for parametric and sensitivity studies. - Leverage a solid understanding of semiconductor manufacturing, advanced‑packaging technologies, material properties, and associated design and reliability constraints. - Design, execute, and interpret validation experiments that correlate and calibrate simulation models with empirical data. - Contribute effectively both independently and as a member of cross‑functional, cross‑cultural, and globally distributed teams. What You Bring - Ph.D. in Mechanical Engineering, Materials Science, Physics, or a related field. (Equivalent combination of a Master's degree and extensive professional experience also welcomed). - 3+ years of hands‑on modeling and simulation experience in the high‑tech or semiconductor industry. - Proven expertise with leading simulation tools such as ANSYS, Abaqus, HyperMesh, and their associated pre‑/post‑processing software. - Proficiency in thermal‑analysis platforms Flotherm and Icepak, together with related utilities. - Extensive experience in static and dynamic simulations, covering linear and nonlinear analyses. - Deep knowledge of design strategies for advanced packaging solutions. - In‑depth understanding of advanced semiconductor packaging, interconnect structures, and reliability‑modeling techniques. - Strong technical‑writing skills, capable of producing clear, comprehensive documentation and communicating complex concepts to both technical and non‑technical audiences. - You're inclusive, adapting your style to the situation and diverse global norms of our people. - An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. - You're collaborative, building relationships, humbly offering support and openly welcoming approaches. - Innovative and creative, you proactively explore new ideas and adapt quickly to change. What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. - Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. - Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. - Care for Family including fertility care or adoption support, medical travel support, and virtual vet care. - Prioritize Emotional Wellness with on-demand apps and free confidential therapy sessions. - Stay Fit with onsite café and gym, plus virtual classes. - Embrace Flexibility with a flexible work environment. Base Pay Range $163,000—$253,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel. Our Commitment to Innovation and Fairness At Samsung Semiconductor, AI tools may be used in the recruitment process to enhance efficiency, but all hiring decisions are made by human recruiting teams and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation, grammar, and research, but not for generating submitted content or live interview responses. Trade Secret Notice By submitting an application, you agree not to disclose confidential or proprietary information belonging to a current or former employer or other entity.

🏢 Summary: Staff-level CPU Architecture & Performance Research Engineer role focused on analyzing and optimizing RISC-V CPU microarchitecture performance using architectural models, simulators, and workload analysis. The position involves collaboration with architecture, compiler, and system teams to identify bottlenecks, evaluate trade-offs, and improve next-generation CPU core performance. Candidates will work on performance-critical domains, contribute architectural recommendations, and support patent and publication work. 🗂️ Requirements: Master’s degree in Computer Engineering, Computer Science, or related field with 8+ years of experience or PhD with 5+ years of experience, 5+ years of CPU microarchitecture or performance engineering experience, Experience with RISC-V, ARM, or X86 architectures, Knowledge of out-of-order execution, branch prediction, pipelines, and speculation, Knowledge of cache coherence, memory systems, prefetching, and NUMA effects, Hands-on experience with architectural simulators, Strong C/C++ programming skills, Strong Python programming skills, Experience analyzing large performance datasets and traces, Familiarity with compiler optimizations and hardware/software co-design, Prior tapeout experience 📃 Skills: RISC-V, ARM, X86, gem5, C, C++, Python, NUMA, SIMD, VME 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. This opportunity focuses on next-generation CPU architecture and performance optimization. What You'll Do Architecture Research Lab is looking for a Staff CPU Architecture & Performance Engineer to drive detailed performance analysis and architectural optimization for current and next-generation CPU (RISC-V) cores. This role focuses on deep ownership of performance-critical micro-architectural domains, workload analysis, and data-driven recommendations that influence core architecture decisions. You will work closely with architects, design, compiler, and system teams to evaluate trade-offs, identify bottlenecks, and improve performance across real-world workloads. Responsibilities - Own performance analysis for one or more CPU microarchitectural domains (e.g., frontend, execution engine, memory subsystem) - Build, extend, and validate architectural performance models and simulators - Perform CPI/IPC breakdowns and root-cause performance bottlenecks - Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models - Characterize workloads and benchmarks (SPEC, server, client, AI/ML, internal traces) - Translate performance data into clear architectural recommendations - Contribute to work leading to patents and publications What You Bring - Master’s degree in Computer Engineering, Computer Science, or related field with 8+ years of experience, or PhD with 5+ years of experience - 5+ years of experience in CPU microarchitecture and/or performance engineering - Experience with RISC-V, ARM, or X86 architectures - Strong understanding of: - Out-of-order execution, branch prediction, pipelines, and speculation - Cache coherence, memory systems, prefetching, and NUMA effects - Hands-on experience with architectural simulators such as gem5 - Strong programming skills in C/C++ and Python - Experience analyzing large performance datasets and traces - Familiarity with compiler optimizations and hardware/software co-design - Proven prior tapeout experience Preferred Qualifications - Background in power/performance/area (PPA) trade-off analysis - Experience or familiarity with SIMD, vectors, or VME for AI inference workloads - Prior leadership experience guiding junior engineers - Prior patent or publication experience Benefits - Competitive compensation with incentive opportunities - Medical, Dental, Vision, and 401(k) - Charitable giving match and community involvement opportunities - 4+ weeks of paid time off, holidays, and sick leave - Fertility care, adoption support, medical travel support, and virtual vet care - Emotional wellness support including confidential therapy sessions - Onsite café, gym, and virtual fitness classes - Flexible work environment and wellness-focused benefits Base Pay Range: $163,000—$253,000 USD

🏢 Summary: Senior RFIC engineer role focused on designing low-power RF and analog integrated circuits for next-generation RF transceivers and mixed-signal systems using advanced CMOS technologies. The position involves chip-level verification, production support, collaboration with digital/software teams, and research into advanced wireless techniques. Extensive experience in RF/analog IC design and strong expertise with RF CAD tools are required. 🗂️ Requirements: Bachelor's degree with 20+ years, Master's degree with 18+ years, or PhD with 15+ years in related field, Hands-on experience designing RF/Analog ICs such as LNA, Mixer, RF VGA, PA, and VCO, Experience with deep sub-micron CMOS technologies, Ability to translate RF transceiver system requirements into circuit specifications, Technical leadership and mentoring experience, Post-silicon validation expertise, Knowledge of IC design CAD tools, Understanding of physical layout requirements and ability to perform critical layouts 📃 Skills: RFIC, CMOS, LNA, Mixer, VGA, PA, VCO, SerDes, DDR, Spectre, SpectreRF, Spice, Matlab, ADS 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. Advanced Circuit and Systems (ACAS) is looking for a highly skilled engineer with a strong background and hands-on experience in RFIC design. The candidate will be developing next-generation RF transceivers and mixed-signal circuits. What You'll Do - Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS technologies. - Lead efforts to perform chain and chip level design verification and production support tasks. - Work closely with digital and software developers to develop implementations that meet system requirements. - Research advanced wireless techniques for highly integrated RFICs. What You Bring - Bachelor's degree with 20+ years of experience, Master's degree with 18+ years of experience, or PhD with 15+ years of experience in a related field. - Hands-on experience designing RF/Analog integrated circuits such as LNA, Mixer, RF VGAs, PA, and VCO in deep sub-micron CMOS technologies. - Ability to comprehend RF transceiver system level requirements and translate them into circuit level specifications. - Excellent problem-solving and analytical skills. - Technical leadership, mentoring, and post-silicon validation expertise. - Specialized knowledge in high-speed I/Os such as SerDes, DDR, or data converters is a bonus. - Strong knowledge of IC design CAD tools such as Spectre, SpectreRF, Spice, Matlab, and ADS. - Thorough understanding of physical layout requirements and ability to perform critical layouts. - Inclusive and collaborative working style with adaptability to diverse global norms. - Curiosity, resilience, and data-driven problem solving. What We Offer - Competitive pay range with incentive opportunities based on individual and company performance. - Medical, Dental, Vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off, holidays, and sick leave. - Family support benefits including fertility care, adoption support, medical travel support, and virtual vet care. - Emotional wellness support with therapy sessions and wellness apps. - Onsite café, gym, and virtual fitness classes. - Flexible work environment. - Base Pay Range: $214,060—$341,940 USD. Equal Opportunity Employment Policy Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process for candidates who require support. Our Commitment to Innovation and Fairness AI tools may be used to support recruitment efficiency, but all hiring decisions are made by human recruiting teams and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation, grammar, and research, but not for generating submitted content or live interview responses. Trade Secret Notice Applicants must not disclose confidential or proprietary information belonging to current or former employers. Applicant Privacy Policy https://semiconductor.samsung.com/about-us/careers/us/privacy/

🏢 Summary: Staff Engineer role focused on end-to-end SRAM circuit design for advanced semiconductor technologies, including development of high-performance, low-power memory arrays for AI, mobile, and computing platforms. The position involves circuit design, simulation, physical verification, methodology automation, silicon bring-up support, and mentoring engineers. Candidates are expected to have deep expertise in SRAM architecture, advanced process nodes, and semiconductor device physics. 🗂️ Requirements: Bachelor's degree in Electrical Engineering with 10+ years of experience or Master's degree with 8+ years of experience, Experience in SRAM or memory circuit design, Proven delivery of SRAM designs in advanced process nodes, Knowledge of semiconductor device physics, Expertise in SRAM architecture and control circuits, Experience with timing analysis and power analysis, Proficiency with circuit simulation and design tools, Knowledge of scripting for automation, Experience with advanced technology nodes such as 5nm or 3nm, Experience with low-power SRAM design techniques, Background in silicon debug and root-cause analysis 📃 Skills: SRAM, HSPICE, Finesim, Spectre, Cadence, Virtuoso, Python, Perl, TCL, FinFET, GAA, SOI, DRC, LVS, DFM 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions. In this position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms. This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design. - Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm). - Optimize SRAM designs for performance, power and area (PPA) and yield. - Develop custom layouts and perform physical design verifications (e.g., DRC, LVS). - Evaluate trade-offs between speed, power, and area to meet design targets. - Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification. - Work with product and test engineers to develop test plans and support silicon bring-up. - Mentor junior engineers, providing guidance on SRAM design techniques and best practices. - Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance. - Contribute to patents, technical papers, or industry conferences to advance SRAM technology. What You Bring - Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred. - Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes. - Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.). - Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths. - Familiarity with timing analysis, power analysis, and design for manufacturability (DFM). - Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc. - Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks. - Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams. - Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond). - Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling). - Background in silicon debug and root-cause analysis. What We Offer - Competitive base pay range: $163,000—$253,000 USD. - Incentive opportunities based on individual and company performance. - Medical, Dental, Vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off, holidays, and sick leave. - Family support benefits including fertility care, adoption support, medical travel support, and virtual vet care. - Emotional wellness support with on-demand apps and therapy sessions. - Onsite café, gym, and virtual fitness classes. - Flexible work environment. Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel. Our Commitment to Innovation and Fairness AI tools may be used to support recruitment efficiency, but all hiring decisions are made by human recruiters and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation and research, but not for generating submitted content or live interview responses. Trade Secret Notice By submitting an application, candidates agree not to disclose confidential or proprietary information belonging to current or former employers.