New offer - be the first one to apply!
July 2, 2026
Staff Engineer, Firmware Test
Senior • On-site
San Jose, CA
Please Note: To provide the best candidate experience amidst high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Description
Our technology solutions power devices and infrastructure including smartphones, electric vehicles, hyperscale data centers, and IoT devices. The Technology Enabling Development Lab (TED) focuses on the host interface firmware layer between system software and flash management firmware, enabling enterprise-class applications and advanced V-NAND technology.
Daily onsite presence is required at the San Jose, CA office in alignment with the Flexible Work policy.
What You'll Do
- Develop black-box functional test coverage and test methodologies for NVMe SSDs.
- Debug and triage failures while working with the firmware team to reproduce issues, design experiments, and validate solutions.
- Analyze customer field issues and improve functional test coverage where gaps are identified.
What You Bring
- Bachelor's degree with 10+ years or Master's degree with 8+ years in Computer Science, Computer Engineering, Electrical Engineering, or equivalent.
- Strong programming and scripting experience with Python, Bash, and Linux shell scripting.
- Excellent verbal and written communication skills.
- Ability to work independently and collaboratively in teams.
- Knowledge of NVMe, PCIe, NAND Flash/FTL, or related storage technologies.
- Experience with enterprise storage or server systems and proficiency in Linux.
Benefits
The compensation package includes incentive opportunities tied to individual and company performance.
- Medical, Dental, Vision, and 401(k)
- Charitable giving match and community involvement opportunities
- 4+ weeks paid time off plus holidays and sick leave
- Fertility care or adoption stipend, medical travel support, and virtual vet care
- On-demand wellness apps and confidential therapy sessions
- Onsite café and gym plus virtual fitness classes
- Flexible work environment
Compensation
Base Pay Range: $163,000—$253,000 USD
Equal Opportunity Employment Policy
Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support.
Our Commitment to Innovation and Fairness
AI tools may be used in the recruitment process to enhance efficiency, but all hiring decisions are made by human recruiting teams and hiring managers.
Applicant AI Use Policy
Candidates may use AI tools for preparation, grammar, and research, but not for generating submitted content or live interview responses.
Trade Secret Notice
By submitting an application, candidates agree not to disclose confidential or proprietary information belonging to current or former employers or other entities.
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Good understanding of PPA (performance, power, and area) trade-offs. Experience in SoC level synthesis, timing analysis, lint check, CDC checks. Experience in interfacing 3rd party service companies for DFT/PI/PD. Good knowledge and experience in AMBA bus fabric, ARM cores. Self-motivated problem-solver with an ability to work well in a team. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. 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New offer

Samsung
Staff Engineer, High-Speed I/O Analog-Mixed Circuit
Senior
On-site
San Jose, CA
🏢 Summary: Senior mixed-signal/analog design role focused on high-speed memory I/O interfaces and advanced CMOS technologies. The position involves analog circuit design, simulations, layout guidance, verification, and silicon bring-up for technologies such as DDR, LPDDR, GDDR, and HBM. Candidates will work on PLL, SERDES, and high-speed data converter solutions supporting next-generation machine learning and data-centric applications. 🗂️ Requirements: BS/MS/PhD in Electrical Engineering or Computer Science, 5+ years in SoC architecture and analog mixed-signal circuit design, Experience with high-speed serial interfaces, Experience with DDR, LPDDR, GDDR, or HBM I/O interfaces, Expertise in high-speed circuit layout requirements, Knowledge of DLL, PLL, FFE, CTLE, DFE, ODT, DCC, and training/calibration, Experience with advanced CMOS technology nodes, Experience with high-frequency clock distribution design, Understanding of PPA trade-offs, Proficiency with EDA tools, Experience with silicon bring-up and automated measurements, Strong Tcl/Perl scripting skills, Ability to work onsite in San Jose 📃 Skills: DDR, LPDDR, GDDR, HBM, SERDES, PLL, DLL, FFE, CTLE, DFE, ODT, DCC, CMOS, Cadence, MATLAB, Simulink, Python, Tcl, Perl, EDA 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Memory IO Lab is part of the Memory Business Unit focused on memory interface technology solutions for DDR, LPDDR, GDDR, and related technologies. The team works closely with cross-disciplinary development teams to bring feature innovation to product roadmaps supporting machine learning applications, data analytics, and edge computing. Location: Daily onsite presence at the San Jose headquarters in alignment with the Flexible Work policy. What You'll Do - Hands-on analog circuit design including circuit implementation, simulations, and verification collaboration. - Work on mixed-signal designs including high-speed data converters, PLL, and SERDES. - Guide layout floor-planning at block and top level to optimize performance. - Supervise layout activities and provide guidelines to layout engineers. - Participate directly in layout drawing when necessary. - Own circuit and system specifications. - Simulate designs using advanced CAD tools. - Document designs and simulation results. What You Bring - BS with 10+ years, MS with 8+ years, or PhD with 5+ years of experience in Electrical Engineering or Computer Science. - 5+ years of experience with system-on-chip architecture, high-speed serial interfaces, and analog mixed-signal circuit design using advanced CMOS technology nodes. - Prior experience designing standard high-speed interfaces such as DDR, LPDDR, GDDR, or HBM I/O interfaces. - Expertise in layout requirements for high-speed circuits. - Knowledge of DLL, PLL, FFE, CTLE, DFE, output drivers, ODT, DCC, training/calibration, high-speed power design, and low-power design. - Experience working with device/process teams to define transistor specifications. - Ability to troubleshoot and analyze complex problems. - Experience in high-frequency clock distribution design, implementation, and analysis. - Deep understanding of performance, power, and area trade-offs. - Ability to use EDA tools such as Cadence, MATLAB/Simulink, and EM tools. - Experience with silicon bring-up and automated measurement scripting. - Strong scripting and automation skills using Tcl/Perl; Python knowledge is a plus. - Strong communication and interpersonal skills. - Ability to work in a fast-moving, dynamic environment. What We Offer - Competitive base pay range of $163,000—$253,000 USD. - Incentive opportunities based on individual and company performance. - Medical, dental, vision, and 401(k) benefits. - Charitable giving match and community involvement opportunities. - 4+ weeks of paid time off plus holidays and sick leave. - Family support benefits including fertility care, adoption support, and medical travel support. - Emotional wellness resources including confidential therapy sessions. - Onsite café, gym, and virtual wellness classes. - Flexible work environment and wellbeing-focused benefits. Equal Opportunity Employment Policy Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process for candidates requiring support. Our Commitment to Innovation and Fairness AI tools may be used during recruitment as support tools only. Hiring decisions are made by recruiting teams and hiring managers. Applicant AI Use Policy Candidates are expected to rely on their own knowledge and skills during the application and interview process. AI tools may only be used for preparation, grammar, and research. Trade Secret Notice Applicants agree not to disclose confidential or proprietary information belonging to current or former employers.
Technology
New offer

Samsung
Manager, Memory Sales
Mid
On-site
San Jose, CA
🏢 Summary: Sales management role focused on revenue growth, customer strategy, market analysis, and demand forecasting in a B2B technology environment. The position involves developing sales execution plans, managing customer relationships, analyzing market and competitor data, and supporting long-term sales agreements and bidding strategies. Daily onsite presence in San Jose is required. 🗂️ Requirements: Bachelor's degree, Minimum 2 years of related experience or advanced degree, Experience with market, customer, and competitor analysis, Ability to analyze short-, mid-, and long-term demand projections, Experience supporting sales strategies, LTA, MOU, trade, and bidding processes, Ability to manage internal resource discussions and coordination, Daily onsite presence in San Jose, CA 📃 Skills: Sales, Forecasting, Analytics, Bidding, CRM, Reporting, Negotiation, Planning 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do • Promote revenue maximization by developing and executing response plans for market changes and sales targets. • Expand the win-win business model through customer trait analysis and management. • Provide and organize data for all processes in achieving target revenue through goal setting, execution, and risk management. • Plan and improve customer satisfaction through meetings, events, and active response to customer needs. • Identify new customers. • Analyze projection data for short-, mid-, and long-term demand through market, customer, and competitor analysis. • Collect and provide data for annual sales strategies such as LTA (Long Term Agreement), MOU (Memorandum Of Understanding), short-term trade, and bidding. • Carry out internal resource discussion and management. Location: Daily onsite presence at the San Jose, CA office in alignment with the Flexible Work policy. Reports to: Senior Director, B2B Sales Management. What You Bring • Develops professional expertise by complying with company policies and procedures. • Works on problems of moderate scope where analyzing situations or data requires review of various factors. • Exercises judgment within defined procedures and practices to determine appropriate action. • Receives general instructions on routine work and detailed instructions on new assignments. • Requires a bachelor's degree with a minimum of 2 years related experience, or an advanced degree without experience. What We Offer • Competitive compensation with incentive opportunities based on individual and company performance. • Medical, Dental, Vision, and 401(k) benefits. • Charitable giving match and community involvement opportunities. • 4+ weeks of paid time off, holidays, and sick leave. • Fertility care or adoption stipend, medical travel support, and virtual vet care. • On-demand wellness apps and free confidential therapy sessions. • Onsite café and gym, plus virtual fitness classes. • Flexible work environment. Base Pay Range: $152,000—$236,000 USD Equal Opportunity Employment Policy Samsung Semiconductor is committed to providing equal employment opportunities and fostering an inclusive workplace. Accommodations are available throughout the recruiting process for candidates with disabilities, long-term conditions, neurodivergence, or pregnancy-related support. Our Commitment to Innovation and Fairness AI tools may be used to support recruitment efficiency, but all hiring decisions are made by human recruiters and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation, grammar, and research, but not for generating submitted content or live interview responses. Trade Secret Notice By submitting an application, candidates agree not to disclose confidential or proprietary information belonging to current or former employers or other entities.
Technology

Samsung
Senior Staff Engineer, SOC Design
Senior
On-site
Folsom, CA
🏢 Summary: Senior SoC Architect role focused on designing and validating next-generation memory and storage solutions, with hands-on RTL development and full lifecycle involvement from architecture to silicon bring-up. The position centers on SSD and DRAM subsystem architecture, SoC integration, and performance optimization for cloud and data center applications. 🗂️ Requirements: Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Science or related field, 10+ years of industry experience in hardware development, Strong experience in SSD architecture and storage technologies, Knowledge of DRAM architecture and memory subsystem design, Experience with RTL design and SoC integration, Experience with data integrity and protection mechanisms (ECC, parity, CRC, RAID), Experience delivering hardware products from architecture through silicon bring-up, Ability to support verification, validation, and debugging activities 📃 Skills: SystemVerilog, Verilog, RTL, SoC, SSD, DRAM, NAND, ECC, CRC, RAID, RTL, Simulation, Emulation, Formal, Silicon 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll Do The DRAM Development Lab (DDL) is part of Samsung's Memory Business Unit, the industry's technology and volume leader in DRAM, HBM and NAND Flash. DDL's vision is to solve key problems of Cloud & Data center by developing the new technology for memory and storage. The SoC Architecture team is involved in SoC‑level designs for emerging memory/storage solutions and validates each design's feasibility with hands‑on RTL implementation. We are an integral part of Samsung's strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. This role offers the opportunity to shape next-generation SoC and subsystem architectures while staying deeply hands-on in RTL design, integration, and validation. It is ideal for engineers who want to turn advanced memory and storage concepts into real hardware and drive them all the way to silicon Job ID: 42896 Location: Daily onsite presence at our Folsom office in alignment with our Flexible Work policy Collaborate with architecture, design, verification, and system teams to define and implement SoC features and subsystems Translate architectural requirements into microarchitecture, RTL design, and verification plans Design and develop RTL for SoC blocks and integration logic using SystemVerilog/Verilog Drive block- and SoC-level integration activities, including clocking, reset, power intent, interfaces, and configuration infrastructure Analyze performance, power, area, and timing tradeoffs to deliver efficient and scalable designs Support design verification by debugging issues found in simulation, emulation, formal analysis, and silicon validation Participate in pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis and issue resolution Contribute to technical documentation, block specification, test plans, and design reviews What You Bring Bachelors in Electrical, Computer Science or related with 15+ years of experience or Masters in Electrical, Computer Science or related Science with 13+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 10+ years of Industry experience preferred. Strong technical background in SSD architecture and storage technologies, including controller architecture, NAND/flash behavior, data path design, and system performance consideration. Familiarity with DRAM architecture and memory subsystem design, including memory hierarchy, bandwidth/latency tradeoffs, buffering, and traffic behaviors. Experience with data integrity and protection mechanisms, such as ECC, parity, CRC, RAID, and end-to-end data protection schemes. Experience contributing to complex hardware products from architecture definition through RTL implementation, verification, and silicon bring-up. Proven ability to collaborate effectively across architecture, design, verification, firmware, and validation teams. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$168,000—$268,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/
Technology

Samsung
Staff Engineer, High-Speed I/O Analog-Mixed Circuit
Senior
On-site
San Jose, CA
🏢 Summary: Senior Analog/Mixed-Signal IC Design Engineer responsible for developing high-speed memory I/O circuits for advanced DRAM and NAND interfaces. The role involves hands-on design, simulation, layout supervision, and silicon bring-up for high-speed data converters, PLLs, and SERDES in advanced CMOS nodes. You will own circuit specifications and optimize performance, power, and area for next-generation memory interfaces. 🗂️ Requirements: BS/MS/PhD in Electrical Engineering or Computer Science, 5+ years in SoC architecture and high-speed serial interface design, Experience with analog and mixed-signal circuit design in advanced CMOS nodes, Experience designing high-speed interfaces (DDR, LPDDR, GDDR, or HBM), Expertise in high-speed I/O layout requirements, Knowledge of DLL, PLL, FFE, CTLE, DFE, DCC, ODT, output drivers, Experience with high-frequency clock distribution design, Proficiency with EDA tools for simulation and verification, Experience with silicon bring-up and automated measurement, Strong scripting skills in Tcl or Perl 📃 Skills: CMOS, SoC, DDR, LPDDR, GDDR, HBM, SERDES, PLL, DLL, FFE, CTLE, DFE, DCC, ODT, Cadence, MATLAB, Simulink, Tcl, Perl, Python, EDA 🏢 Description: Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.Memory IO Lab is part of Samsung's Memory Business Unit, the industry's all-time DRAM and NAND Flash leader both in technology as well as in volume. Memory IO's vision is to provide memory interface technology solutions which can be adopted in DDR, LPDDR, GDDR, and more. We are an integral part of Samsung's paramount R&D innovation engine. We work closely with cross-disciplinary development teams to bring feature innovation to product roadmaps. Come and join the team that is providing the next generation IO tech solutions to support emerging machine learning applications, data analytics, and edge computing. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work policy What You'll Do Hands on in analog circuit design, which includes circuit design, running simulations to confirm functionality and performance, and work with verification team to verify design. The mixed-signal designs will include but are not limited to the following: high-speed data converters, PLL, and SERDES. Guide layout floor-planning block and top level to optimize the overall performance; supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary. Ownership of circuit and system specifications. Simulate designs with state-of-the-art CAD tools. Document designs and simulation results. What You Bring BS 10+ years experience, MS 8+years of experience, PhD 5+ years experience in Electrical Engineering, Computer Science preferred. 5+ years of experience working with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes. Prior experience in design of any one of the standard high speed interfaces like DDR, LPDDR, , GDDR, HBM I/O interface. Needs to be an expert in providing and understanding layout requirements of high speed circuits. Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design. Experience working closely with device/process team to define transistor specs The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment. Ability to troubleshoot and analyze complex problems. Excellent communication (written and verbal) and interpersonal skills Experience in high frequency clock distribution design, implementation, and analysis. Deep understanding of PPA (performance, power, and area) trade-offs. Ability to handle EDA tools well, such as Cadence, MATLAB (Simulink), and EM tools Experience on silicon bring-up and automatic measurement using script Strong scripting and automation skills using Tcl/Perl. Knowledge of Python is a plus. Self-motivated problem-solver with an ability to work well in a team. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-SF1What We OfferThe pay range below is for all roles at this level across all US locations and functions. Paywithin this range varies by work locationand may also depend on job-related knowledge, skills,and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are.Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you.Base Pay Range$163,000—$253,000 USDEqual Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policyhttps://semiconductor.samsung.com/about-us/careers/us/privacy/
Technology
New offer

Samsung
Staff Engineer, Memory Systems Architecture
Senior
On-site
San Jose, CA
🏢 Summary: Staff Engineer role focused on memory systems architecture and in-field DRAM fault management for AI/ML data center deployments. The position involves analyzing telemetry data, developing RAS algorithms, improving ECC schemes, and collaborating with customers and industry groups on memory failure mitigation solutions. Daily onsite work in San Jose with research, proof-of-concept development, and standardization contributions. 🗂️ Requirements: Bachelor's degree with 10+ years of relevant experience or Master's with 8+ years or PhD with 5+ years, Experience in hardware fault management, reliability, or data center fleet management, Knowledge of platform memory subsystems and platform RAS features, Experience with ECC design, verification, and reverse engineering, Understanding of CPU-to-memory address mapping, Experience modifying memory controller registers, Linux kernel commit experience, Understanding of DRAM and HBM failure modes 📃 Skills: DRAM, HBM, ECC, RAS, Linux, Telemetry, hPPR, DIMM, SOC 🏢 Description: Advancing the World's Technology Together Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and more. Samsung Semiconductor is hiring a Staff Engineer, Memory Systems Architecture. The conventional DRAM failure analysis was physical electrical FA and physical FA. In the era of data centers, field failure information is easier to track. The Fault Management team focuses on finding DRAM failure modes, abnormalities, and failure rate projections. You will be part of an incubation team working on in-field telemetry intended to transform the customer quality experience for Samsung memory products. Fault Management is focused on minimizing system downtime within AI/ML hardware deployments and workloads. The team analyzes trends and patterns from large-scale memory fleet telemetry to classify failures and perform virtual root-cause analysis. Telemetry analysis helps design solutions to proactively avoid system downtime. Research is conducted both internally and collaboratively with the industry, with opportunities to publish findings through whitepapers and conferences. What You'll Do - Based on knowledge of SOC controllers and memory operations including RAS features, identify and recommend solutions to mitigate field DRAM failure rates - Communicate improved ECC schemes to customers based on Samsung DRAM failure modes - Interface with customers to establish the value of enabling in-field fault management architecture - Contribute to the standardization of DRAM/HBM failure logging in the OCP - Propose and develop platform RAS algorithms for memory fault management such as page offlining and hPPR - Conduct proof-of-concept testing with known failure DIMMs in real servers and applications Location: Daily onsite presence at the San Jose headquarters in alignment with the Flexible Work Policy. What You Bring - Bachelor's degree with 10+ years of relevant industry experience, or Master's with 8+ years, or PhD with 5+ years in hardware fault management, reliability, data center fleet management, or related technical field - Knowledge of platform memory subsystems and platform RAS such as ECC, page offlining, hPPR, and hardware sparing - ECC design, verification, and reverse engineering experience - Understanding of address mapping between CPU and memory - Memory controller register modification experience - Linux kernel commit experience - Understanding of DRAM and HBM failure modes - Inclusive and collaborative working style - Curiosity, resilience, and data-driven problem solving - Innovative mindset and adaptability What We Offer - Competitive compensation with incentive opportunities - Medical, dental, vision, and 401(k) benefits - Charitable giving match and community involvement opportunities - 4+ weeks of paid time off plus holidays and sick leave - Fertility care or adoption support, medical travel support, and virtual vet care - Emotional wellness support with therapy sessions and wellness apps - Onsite café and gym plus virtual fitness classes - Flexible work environment Base Pay Range: $163,000—$253,000 USD Equal Opportunity Employment Policy Samsung Semiconductor is committed to fostering an inclusive workplace and providing accommodations throughout the recruiting process. Our Commitment to Innovation and Fairness AI tools may be used in recruitment as support tools, but all hiring decisions are made by human recruiters and hiring managers. Applicant AI Use Policy Candidates may use AI tools for preparation, grammar, and research, but not for generating submitted content or live interview responses. Trade Secret Notice Applicants must not disclose confidential or proprietary information belonging to current or former employers.