SoC Performance Modeling Software Engineer (Platform Architecture)
Apple
Austin, TX • 13m ago • On-site
Senior
On-site
184,700 - 277,600 USD/yr
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Potential salary for SoC Performance Modeling Software Engineer (Platform Architecture) role
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$184,700 – $277,600/year
Quick Facts
Role: SoC Performance Modeling Software Engineer (Platform Architecture)
Focus: Performance models and simulator infrastructure for system-on-chip hardware
Description
In this role, you will be part of the system-on-chip (SoC) performance team working with SoC architecture, design, power, and software groups to deliver world-class cache and memory system performance. You will build and evolve performance modeling software that translates design space studies into well-written models, supporting the full life cycle—from early architectural exploration to post-silicon correlation. You will also improve simulator performance, maintainability, and flexibility so hardware architects can iterate on experiments quickly.
Responsibilities
Leverage C++ to maximize the utility of performance modeling software models
Develop APIs that can be used by non-expert C++ developers
Train AI agents and non-expert C++ developers on idiomatic code and methods
Ensure the codebase is structured for effective use with AI-assisted development tools
Write clear, self-documenting code with consistent conventions, meaningful naming, and well-organized modules
Learn and apply the state of the art in SoC IP and chip-level architecture
Work on data analysis pipelines, visualization methodologies, and continuous regression testing
Run performance simulations and carefully analyze and present simulation results
Requirements
Bachelor’s degree
Experience with hardware architecture and design issues
Experience coding in C++ and Python
Experience with computer architecture and software engineering principles
Experience with data structures and algorithms
Benefits
Collaboration across SoC architecture, design, power, and software teams to enable seamless CPU, GPU, machine learning, camera, display, and connectivity performance on chip platforms
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