Senior Package Design Engineer

Quick Facts

• Senior Package Design Engineer focused on 2.5D/3D semiconductor packaging for Azure datacenter silicon.
• End-to-end ownership from definition to tapeout with SI/PI and PCB/DFT/ATE co-design and signoff.
• Coordination across internal teams and external suppliers to enable advanced packaging technologies.

Description

The Senior Package Design Engineer will own and execute custom silicon package designs (substrate, interposer, bridge) across the full product life cycle, from definition to tapeout. You will drive package architecture and floorplans for chiplet-based designs using advanced packaging technologies such as CoWoS and HBM integration, and perform package–PCB co-design to meet system-level specifications. The role includes signoff (DRC, LVS, LEC, DFM), maintaining traceable design data, managing connectivity/netlists across ECOs, and supporting evaluation of new packaging technologies.

Responsibilities

• Own 2.5D/3D package designs (substrate, interposer, bridge) from definition to tapeout
• Develop package architecture and floorplans for chiplet-based designs using CoWoS and HBM integration
• Drive package and PCB co-design: define BGA ballout and bump plans; optimize floorplans with SI/PI, silicon PD/RTL, PCB, DFT, and ATE teams
• Perform package layout and routing in industry-standard EDA tools (Cadence APD/Allegro); develop scripts and automation
• Run package design signoff (DRC, LVS, LEC, DFM) and close issues before tapeout
• Define and maintain package design requirements and specs; keep design data/versions/documentation complete and traceable
• Balance trade-offs with silicon/platform architects and thermal, power, and performance engineers
• Evaluate and recommend new packaging technology and support device/package qualification and supplier assessment
• Work with external partners (OSATs, substrate/interposer suppliers, design-service partners) on rules, reviews, and tapeout deliverables
• Help design test vehicles to validate new package technologies and design rules
• Identify design risks early in new technology/tool flows; propose mitigations and report status
• Manage die-to-interposer-to-substrate connectivity and netlists across multi-die designs; keep synchronized through ECOs
• Design the package power delivery network (planes, layer stack-up, decoupling placement) with PI engineers
• Generate and deliver package design data and extracted models to SI/PI, thermal, and board teams; iterate from results
• Evaluate/improve package design flows and methods; review designs and mentor engineers

Requirements

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 1+ year(s) technical engineering experience, or Master’s with 4+ years, or Bachelor’s with 5+ years, or equivalent experience
• Ability to pass required security screenings, including the Microsoft Cloud Background Check, and to verify citizenship/residency for export-controlled information access