Chipset Power Architect, Devices and Services, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
  
• 8 years of experience in power management or low power design/methodology.
  
• Experience with low power architecture and power optimization techniques (e.g., multi Vth/power/voltage domain design, clock gating, power gating, Dynamic Voltage Frequency Scaling (DVFS, AVS)).
  
• Experience with full product delivery cycle (e.g., definition, architecture, design and implementation, testing, productization).
  

Preferred qualifications:

• Master's degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
  
• Experience with SoC power modeling and analysis.
  
• Knowledge of ASIC design flows.
  
• Excellent written and verbal communication skills, with the ability to work across cross-functional teams to drive consensus and influence product decisions.
  

About the job

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead the definition of power requirements for Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints.
  
• Define power Key Performance Indicators and SoC/IP-level power goals, and lead cross-functional architecture, design, implementation and software teams to achieve power goals in volume production.
  
• Model system on a chip (SoC) and IP-level power and perform power rollups.
  
• Propose and drive power optimizations throughout the design process from concept to mass productization.
  
• Drive power-performance trade-off analysis for engineering reviews and product roadmap decisions and represent status of SoC power to leadership team.