Senior Test Engineer, CMOS Backplane, Raxium

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, or a related field or equivalent practical experience.
• 4 years of experience with Silicon, CMOS, and IC test development.
• 3 years of experience with Silicon test hardware, software debugging, and data analysis in a reasearch and development or manufacturing environment.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
• Experience with testing software development, Python, and SQL databases, with the knowledge of Linux and Ubuntu.
• Familiarity with test instruments such as power supply, current meter, voltage meter, digital meter, spectrometer, and other electrical lab equipment.
• Familiarity with firmware concepts, low-level register programming (bare metal programming in C/C++ for microcontrollers), I2C and SPI, and SRAM memory test patterns.
• Knowledge of electrical engineering fundamentals (CMOS and register-level understanding), power management, display architecture, and video standards such as HDMI or MIPI.

About the job

As a Senior Test Engineer for CMOS Backplane, you will be responsible for the test development of the CMOS Backplane in the microLED-based Display Panel solutions. This role interfaces with the CMOS Backplane Development and Panel Test teams to develop custom test solutions for our next-generation display panels. You will work closely with the Display Panel test development engineers and operations team to ensure optimal test time, capability, capacity, and cost for engineering and production test plans.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $147,000-$216,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Develop, validate, and optimize standards and engineering CMOS Backplane test solutions for microLED display panels, including CMOS control software solutions. Ensure software test platform and architecture meet the needs of production and research and development environments, to ensure high uptime of the test operations.
• Interface with wafer-level probe cards, test equipment, and instrumentation to facilitate CMOS/Silicon testing and characterization.
• Identify, diagnose, and resolve electrical issues during wafer-level testing using digital oscilloscopes and other testing equipment.
• Collaborate with CMOS and panel test engineering teams to define and implement automated testing solutions for IC/Silicon/CMOS and microLED displays, and debug process plans for manufacturing. Optimize these solutions to ensure test coverage and minimize the test cost.
• Work with the Test Engineering team to enhance and develop test frameworks based on requirements from the Reliability Team.