Signal and Power Integrity Engineer, PhD, University Graduate

Minimum qualifications:

• PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• Experience with Signal and Power Integrity (SI/PI) fundamental concepts, microwave theory, or analog circuit design.

Preferred qualifications:

• Experience in AMS (Analog Mixed Signal) design.
  
• Experience in Matlab, Python, C++ to establish automation flows and data processing.
• Experience with SIPI or microwave modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc.).
• Experience with Signal and Power Integrity (SI/PI) analysis and design for high-speed digital systems, including chip-package co-design concepts.
  
• Excellent programming and data analysis skills.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Signal Integrity/Power Integrity Engineer, you will lead chip and package design, ensuring optimal Signal Integrity (SI) and Power Integrity (PI) performance and system co-design from concept to production. You will collaborate within a cross-functional team, including chip design, Intellectual Property (IP), system design, software, and vendors. You will drive signal and power design implementations on chip and advanced packages.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Be responsible for driving chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc., for High-Performance Computing (HPC) based on 2.5D/3D package technology.
  
• Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design goal, define boundaries of chip design and explore SI/PI and Design for Manufacturing (DFM) trade-off for package design closure for production.
  
• Provide feedback on chip floorplan considering package/system routability and SI/PI.
  
• Develop methodology to enhance accuracy and productivity.
  
• Support workflows for post-silicon validation, qualification of high speed interface for New Product Introduction (NPI), high speed Interface IP evaluation (serdes, memory), and high power, large DI/DT power integrity.