ASIC Electrostatic Discharge/Latch-Up Design and Sign-off Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of technical experience in physical design disciplines involving ESD (Electrostatic Discharge)/LU (Latch-Up) and advanced process technology nodes.
• Experience with ESD analysis and signoff.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience owning ESD sign-off and establishing ESD signoff methodologies, and bringing up ESD flows for new projects.
• Experience driving the design for ESD convergence.
• Experience in evaluating and selecting IP based on ESD considerations.
• Knowledge of PowerEdge Raid Controller (PERC) checks, analysis and post silicon ESD and LU stresses.
• Knowledge of silicon development milestones.

About the job

As an Electrostatic Discharge (ESD) and Latch-Up (LU) sign-off Engineer, you will collaborate cross functional from IP selection to System design and everything in between to meet the needs of advanced technology nodes and deliver ASIC’s and SoC’s. You will drive engaged and reliable products by optimizing, analyzing, customizing, and verifying our reliability specifications. You will perform technical evaluations of EDA tools, process nodes, and IPs and provide recommendations. You will develop reliability solutions that enable IPs that provide an edge over competition. You will see these products through from inception to maturity to tapeout and mass deployment.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Responsibilities

• Drive design for ESD/LU at full-chip context including but not limited influencing physical design methodologies.
• Influence IP selection by evaluating ESD requirements and formulate correct by construction approach.
• Collaborate with the physical design, floorplan, and package teams to ensure reliability structures are planned and integrated.
• Work with internal teams and external vendors to bring up ESD LU tools (e.g., path-finder, Calibre, ICV) for new projects.
• Contribute to flows, checkers, reporting and any tooling around sign-off.