Physical Design Flow and Methodology Lead

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience with physical design flow and methodologies.
• Experience with EDA tools for physical design.
• Experience in full-chip or block-level physical design.
• Experience with scripting in Python, Tcl, or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience developing and deploying methodologies and Tcl/Python automation to significantly boost Time-to-Market (TTM) and Quality of Results (QoR).
• Experience in sign-off closure techniques, including SSTA, physical verification, EMIR, and low-power implementation (UPF/CPF).
• Experience in integrating and ensuring closure for high-speed IP subsystems.
• Experience with evaluating foundry process nodes, third-party IP, and vendor capabilities to inform long-term strategic decisions and planning.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will have an opportunity to shape the future of Artificial Intelligence/Machine Learning (AI/ML) hardware acceleration by driving TPU technology that powers Google's most demanding AI/ML applications. As part of the Chip Innovation Infrastructure team, you will be at the forefront of developing custom silicon solutions that will power the future of Google's TPU, contributing to the innovation behind products used by millions of people worldwide. Your work will have a worldwide impact, as the products you develop will enable an entire team of people across multiple locations. You will be part of a team that is transitioning to a new chip design methodology, giving you the opportunity to be at the forefront of this change and automate how the team works.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead the effort for timing closure of blocks, subsystems, and fullchip.
• Drive physical implementation steps including synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification on blocks, subsystems or fullchip.
• Work with logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
• Drive physical design methodologies and automation scripts for various implementation steps.
• Perform technical evaluations of vendors, process nodes, IP, and provide recommendations.