Low-Power Design Engineer, ML Accelerators

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 8 years of experience in silicon design, verification, physical design, or post-silicon validation.
• Experience with RTL design using SystemVerilog, Verilog, or similar HDL.
• Experience with power analysis, sign-off, or management.
• Experience with low-power design methodologies or applying power reduction techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 10 years of experience in silicon design, verification, physical design, or post-silicon validation.
• Experience defining and implementing chip-wide power management architectures and designs.
• Expertise in power modeling, measurement, and correlation across the pre- and post-silicon phases.
• Understanding of modern power and thermal management techniques at both the silicon and system levels (including DVFS, Turboing, Thermal Management, and system-level tradeoffs).
• Ability to solve complex, open-ended power and performance problems under ambiguity.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As part of the TPU power design team, you will play a pivotal part in the improving power efficiency of our TPUs. You will drive power efficiency for our TPU designs, starting from building robust power models to proposing novel power optimization techniques. You will utilize background in modeling and optimizing chip power, as well as have an understanding of system level power considerations and tradeoffs.

The AI and Infrastructure team works on the world’s toughest problems, redefining what’s possible and the possible easy. We empower Google customers by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Googler Cloud customers, and billions of Google users worldwide. We’re at the center of amazing work at Google by being the “flywheel” that enables our advanced AI models, delivers computing power across global services, and offers platforms that developers use to build services.

In AI and Infrastructure, we shape the future of hyperscale computing by inventing and creating world-leading future technology, and drive global impact by contributing to Google infrastructure, from software to hardware (including building Vertex AI for Google Cloud). We work on complex technologies at a global scale with key players in the AI and systems space. Join a team of talented individuals who not only work together to keep data centers operating efficiently but also create a legacy of driving innovation by building some of the most complex systems technologies.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Define best practices and methodologies to achieve low-power RTL designs.
• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
• Collaborate with cross-functional software and system teams to create novel power management architectures.
• Contribute to design power modeling and drive convergence to power goals.