Staff ASIC Design Verification Engineer, Platforms and Devices

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 10 years of experience in taking multiple silicon projects from concept to product release.
• Experience strategizing and verifying digital logic at RTL and GLS level using SystemVerilog or C/C++ or Universal Verification Methodology (UVM).
• Experience with system-level architecture, scripting languages, Software (SW) development frameworks and their impact on Design Verification (DV).
• Experience creating and using verification components and environments in standard verification methodology from scratch through Tapeout.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• 12 years of experience with building verification methodologies that span simulation, formal, emulation and FPGA prototyping.
• Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).
• Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation.
• Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
• Experience with architectural background in one or more of: Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a tech lead in the Google Silicon Platforms team, you will work on the verification of Googles SOC offerings. You collaborate with hardware architects and design engineers for functional, power and performance verification of the infrastructure Intellectual Properties (IPs), interconnects, caches, memory management and system services.

You will work on solving multi dimensional problems that may be ambiguous and lacking clear precedent. You also work on developing VIPs for protocols supported by our SOCs, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs.

Our approach to building systems is based on scalability. Your work will include building and verifying a generalized system topology abstractions, and developing the associated methodologies and tools needed to solve the problem.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google

Responsibilities

• Develop comprehensive testplans by understanding design specifications and interacting with designers to define verification strategy, scenarios, stimulus, checks, and coverage.
• Develop strategy, effectively navigating ambiguity in the execution and verification of the next generation configurable Infrastructure IPs, interconnects or memory subsystems.
  
• Develop cross language tools and scalable verification methodologies and ensure documentation is comprehensive, can be easily understood and used.
• Collaborate with cross functional teams to debug failures (design, arch, software, post-si, thermal issue etc.) and provide solutions.
• Assess the risk and figure out the mitigation plans to successfully deliver to the project timelines.