ASIC Design Verification Engineer, Devices and Services

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
• 8 years of experience with verifying digital logic at RTL level using SystemVerilog or C/C++
• Experience creating and using verification components and environments in standard verification methodology
• Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems)

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
• Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation
• Experience with building verification methodologies that span simulation, emulation and FPGA prototypes
• Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL)
• Knowledge of scripting languages and software development frameworks
• Architectural background in one or more of the following: Low Power Design, Distributed Systems, DDR/LPDDR, PCIe, Processors and Memory Subsystems, Security, Clock and Power Controllers

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As an ASIC Design Verification Engineer, you will be part of a Research and Development team, and your responsibilities will include building verification components, constrained-random testing, system testing, and verification closure.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Plan and execute the verification of the next generation configurable infrastructure IPs, interconnects, and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Develop cross-language tools and scalable verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct blocks and subsystems, and close coverage measures to identify verification holes and to show progress towards tape-out.