Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 10 years of experience with RTL design using Verilog or System Verilog and microarchitecture.
- Experience leading IP/SoC design for low power SoCs.
- Experience with ARM-based SoCs, interconnects and ASIC methodology.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 5 years of industry experience with IP design for clocking, interconnects, peripherals etc.
- Experience with methodologies for low power estimation, timing closure, synthesis.
- Ability to drive multi-generational roadmap for IP/SoC development.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your experience to be part of the team that designs chassis IPs (NoC, Clock, Debug, QoS etc.) and subsystems for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver high quality RTL design. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance, power and area in mind.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Drive multi-generation roadmap for design optimization, meet schedule commitments and provide support to customers.
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Oversee RTL development, debug functional/performance simulations .
- Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
- Communicate and work with multi-disciplined and multi-site teams.
