Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with IP Development or SoC Integration, from early architecture phase through tapeout.
- 3 years of experience in people management, developing employees.
- Experience in ASIC development with System Verilog.
- Experience in Computer Architecture, including working with CPU cores, GPU Streaming Multiprocessors, or ML accelerator cores.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 12 years of experience with IP Development or SoC Integration, from early architecture phase through tapeout.
- Knowledge of high performance and low-power design techniques.
- Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design.
About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Silicon Design Manager for Tensor Processing Unit (TPU) Compute, you will develop high performance and low power hardware to enable continuous innovations in TPUs. In this role, you will work with Architects and Logic Designers to drive architectural feasibility, establish timing, power and area design goals, and explore RTL/design trade-offs for physical design closure. You will also work with Verification and Software teams to understand and implement the design requirements for clocking and power management.
The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Lead, mentor and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.
- Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
- Serve as the primary point of contact for all design-related activities on projects.
- Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
- Collaborate closely with the cross-functional teams (e.g., Verification, Design for Test, Physical Design and Software) to make design plans and present project status throughout the development cycle.
