Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with Static Timing Analysis.
- Experience with SystemVerilog, or Verilog.
- Experience in silicon validation methodologies, tools, and techniques.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Video Processing.
- Experience in computer aided design software.
- Strong system level understanding.
About the job
Raxium is seeking a highly motivated and skilled Digital Design Engineer with expertise in SystemVerilog to join our innovative team developing micro-LED displays for next-generation Augmented Reality (AR) devices. In this role, you will be instrumental in designing, verifying, and implementing complex digital logic for high-performance display systems.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
Responsibilities
- Design and develop RTL using SystemVerilog for various digital blocks, including display controllers, image processing units, and high-speed interfaces.
- Perform digital simulation and verification using industry-standard methodologies and tools to ensure design correctness and meet performance specifications.
- Collaborate with architects, analog designers, and firmware engineers to define specifications, integrate designs, and troubleshoot issues.
- Contribute to design documentation, including specifications, block diagrams, and verification plans.
