Technology Commodity Manager, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
• 8 years of experience in ASIC/chip design with leadership and technical ownership.
• 8 years of experience with industry-standard EDA tools for RTL simulation, synthesis, and static timing analysis.

Preferred qualifications:

• Experience with design for testability (DFT) concepts and methodologies (scan, JTAG, MBIST).
• Experience with embedded processors (e.g., ARM, RISC-V) and associated peripherals.
• Experience in UVM/OVM or other advanced verification methodologies.
• Knowledge of low-power design techniques.
• Familiarity with scripting languages (e.g., Python, Perl, Tcl) for automation of design flows.
• Understanding of physical design concepts (floor planning, place and route, clock tree synthesis).

About the job

A problem isn’t truly solved until it’s solved for all. That’s why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you’ll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You’ll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.

In this role, you will manage external Outsourced Semiconductor Assembly and Test (OSAT) relationships and collaborate effectively with key suppliers and partners. You will be instrumental in the design, verification, and implementation of complex digital integrated circuits from concept to production, with an emphasis on ensuring seamless integration and outcomes with our external technology providers. You will work on technologies that are critical to our next-generation products, contributing to the life-cycle of ASIC development while actively managing our external technical engagements.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Responsibilities

• Lead vendor selection and oversee activities, including architectural definition, pre-silicon verification, synthesis, and timing closure to meet performance and power goals.
• Integrate Design-for-Test (DFT) features, support physical design for tape-out, and collaborate on post-silicon validation.
• Be responsible for comprehensive documentation, effective team collaboration, proactive problem-solving, and staying current with ASIC design trends for continuous improvement.
• Ensure functional correctness and efficient silicon production from conception to validation.