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July 20, 2025

System Level Test Team Lead, Google Cloud

Senior • On-site

$183,000 - $271,000/yr

Sunnyvale, CA

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with SLT test flow development.
  • Experience in leading initiatives from concept to completion.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • 10 years of experience in System Level Test (SLT) engineering, silicon validation, silicon product engineering and test engineering.
  • Experience with SLT test flow development, test automation, and test deployment actively contributing to technical design and problem-solving.
  • Experience with SLT test handlers from Advantest, Teradyne, Chroma, or others.
  • Experience in Python for test automation and data analysis.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s data centers are the most advanced in the world. In this role you will help build the SoC’s that power these data centers by developing and deploying comprehensive test solutions with Automatic Test Equipment (ATE) for New Product Introduction and hand-off for High Volume Manufacturing at wafer fabs and OSAT’s. This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generations of chips.

You will be a senior technical contributor on the team that drives SLT manufacturing test development and deployment. You will drive hardware development, test integration, test automation, and test deployment. You will work closely with cross functional teams to ensure the optimal test coverage in production to ensure high quality SoCs.

A strong understanding of IC flows, wafer processing, testing, qualification and failure analysis is expected. You will work with various groups to develop tests, automation methodologies, test program release, etc. You will also work on releasing cost effective production test solutions into mass production.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Develop and deploy System Level Test (SLT) solutions for NPI and hand-off to High Volume Manufacturing (HVM), partner with vendors and internal cross-functional teams.
  • Drive hardware and integration requirement specification, software frameworks and test flows, and test case integration from silicon validation and system software teams.
  • Partner with datacenter server and accelerator design teams to realize practical test solutions leveraging system design and test elements.
  • Partner with hardware and software teams to evaluate functional device yield and performance across operating conditions and develop effective production screens to reduce Defective Parts per Million (DPPM).
  • Integrate test software and hardware solutions with SLT handlers, drive NPI bring-up, and transfer all collaterals for HVM at Offshore Assembly and Test (OSAT) facilities, provide ongoing HVM support.