Chiplet Lead, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 8 years of experience in UCIe or Serial PHY Development.
• Experience in custom circuit design and simulation of Analog Mixed-Signal IP.
• Experience with SERDES IP integration such as PCIe, USB, D2D UCIe into SoC from feature definition to full design implementation.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or a related field.
  
• Experience of Pre-silicon to Post-Silicon overall end to end execution of UCIe or high speed Serial PHY.
• Experience in Post-Silicon debug using the latest process technology nodes.
• Experience in developing multiple Analog Mixed-Signal IP.
• Excellent in statistical, data analysis, teamwork and communication skills.

About the job

In this role, you will be responsible for selecting and integrating Chiplet technologies along with other IO interfaces. You will work with vendors for selecting Die to Die IP and ensure it meets the quality of productization. You will ensure pre-silicon and post-silicon qualification of this IP.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Responsibilities

• Engage with industry and vendors to identify Chiplet technologies and select IPs for inhouse technology test chip development.
• Drive requirements for Pre-silicon and Post-Silicon functional and DFT plans.
  
• Work with the Post-Silicon Product Engineering team on Post-Silicon debug, leading to seamless execution from IP sourcing, integration to final post-Silicon verification.
  
• Be responsible for some inhouse IP development like Ring Oscillators and correlation with post-Si data collection.