Static Timing Analysis Engineer, FullChip/ASIC Implementation

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of technical experience in silicon timing closure and chip integration.
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in extraction of design parameters, QoR metrics, and analyzing data trends.
• Experience with high complexity silicon in state-of-the-art technology process nodes.
• Experience with ASIC design flows and methodology of static timing analysis.
• Effective skills with scripting languages such as Tcl or Perl.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Responsibilities

• Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis.
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs. 
• Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area.
• Oversee full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation, and final timing signoff for SoC’s.