ASIC/SoC System Level Test Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of industry experience with System Level Test or System validation.
• Experience with ASIC or SoC prototype bring-up, debug, functional verification, or functional manufacturing test.
• Experience with Python and Linux or Unix.

Preferred qualifications:

• Master's degree/PhD in Electrical Engineering, Computer Engineering or Computer Science.
• 8 years of industry experience with System Level Test, System validation, or Product Engineering.
• Experience with testing and characterizing IP subsystems such as CPUs, GPUs, SerDes, DDR/HBM.
• Knowledge of CPU Architecture, CPU Boot process, Kernel, and CPU performance.
• Experience implementing secure ASIC/SoC manufacturing solutions (provisioning, e-fuse programming, or life-cycle management).
• Experience in C#, .NET Framework, C/C++, or basic TCP/IP network configuration.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a System Level Test Engineer, you will help to integrate SoC (System on Chip) technologies into High Performance Computing Products. You will develop and automate system-level manufacturing test of ASIC’s and SoC’s to validate performance and screen out bad devices. You will participate in all aspects of System level Test and Product Engineering activities. You will work with ASIC Architecture, Design, and Pre-silicon SoC Verification teams to define test methodologies and implement end to end manufacturing solutions.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Develop System Level Test (SLT) solutions for custom ASIC’s and SoC’s by specifying hardware and integration requirements, driving vendor interactions, developing software frameworks and test modules, and integrating test cases from silicon validation and system software and test teams.
• Partner with data center server and accelerator design teams to realize practical test solutions leveraging system design and test elements.
• Partner with hardware and software teams to evaluate functional device yield and performance across various operating conditions, characterize hardware/software interaction, and develop effective production screens to reduce Defective Parts per Million.
• Integrate test software and hardware solutions with robotic chip handlers, drive bring-up of the fully integrated solution in internal and partner NPI labs, transfer all collaterals needed for High Volume Manufacturing (HVM) at Offshore Assembly and Test (OSAT) facilities, and provide ongoing HVM support.