Power Integrity Engineer, Google Cloud

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
  
• 4 years of experience working in a system-level power delivery network design, analysis, and validation technical environment, or 3 years of experience with an advanced degree.
• Experience with power management methodologies, power delivery, and signal integrity interactions of common I/O interfaces.
• Experience with PCB, package and silicon technologies, and their impact on power delivery solutions.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
• 1 year of experience in technical leadership.
  
• Experience in power integrity fundamentals, including board power conversion design for motherboard, data center hardware products, and power integrity conversion design.
• Experience with electronic design automation tools, and 3D/2D electromagnetic simulation tools, lab equipment, and scripting languages.
• Experience with lab measurement, validation and correlation at package, Die, and PCB level.
• Knowledge of system power delivery networks and switching voltage regulator modeling and simulation.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Power Engineer, you will play a key role in the development of one of the computing infrastructures. You will work as part of a team to deliver innovative power solutions for point of load application. Your objective will be to design, analyze, optimize and implement board, substrate package and chip level power topologies and control for large-scale point of load application including ASICs, field-programmable gate array (FPGA) and processors.

The US base salary range for this full-time position is $142,000-$211,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Responsibilities

• Innovate and design on board, on substrate and on chip level Power Delivery Networks (PDN). Analyze performance, cost, reliability and availability design trade-offs.
• Provide technical leadership and direction while troubleshooting complex system level power delivery issues.
• Work cross-functionally with Project teams, on system bring up and design validation.
• Perform lab design validation, correlation study and root cause debugging.