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Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.
Description
Candidates will be responsible for RTL to netlist generation working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Minimum Qualifications
- Experience with at least one of the following scripting languages: python, perl, tcl
- BS required
Preferred Qualifications
- Relevant Coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design
- Familiarity with Verilog and System Verilog
- Exposure to industry standard rtl2gds tools for synthesis, place and route, static timing analysis
- Exposure to Clock/Reset domain crossing or Voltage crossing principles
- Familiarity with DFT methodologies
- Knowledge of static timing analysis concepts (setup and hold timing)
- Understanding of CMOS device characteristics for area/timing/power tradeoffs
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
