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Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.
Description
Candidates will be responsible for PPA optimization of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.
Minimum Qualifications
- Experience with Verilog, System Verilog or other scripting languages
- BS + 3 years of relevant experience
Preferred Qualifications
- Experience with physical synthesis, including logic and PPA optimization techniques
- Experience using logic equivalence tools for RTL and Gate-level designs
- Understanding and application of physical design (PD) and static timing analysis (STA) principles
- Ability to analyze critical paths and guide RTL designs to optimal solutions
- Collaborate effectively with IP teams spanning multiple sites
- Familiarity with DFT insertion
- Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level
- Experience implementing ECOs for functionality and timing
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
