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In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with constructing and modify timing flows, timing analysis, and timing closure.
Description
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:
• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency
• Working extensively with CPU micro-architects and implementation engineers to drive timing closure for the CPU
Minimum Qualifications
- Minimum BS and 3+ years of relevant industry experience
- STA/physical design knowledge of device physics
- Experience with cross talk, noise, OCV or uncertainty
- Knowledge of static timing tools and flows
Preferred Qualifications
- The ideal candidate will have implementation experience on high performance CPU designs including at least one project that includes ownership of timing analysis
- Prior experience owning the timing flow on a major CPU or similar project
- Working knowledge of CPU microarchitecture including common critical loops for timing and understanding of low power microarchitecture and implementation techniques for CPUs
- Good understanding of physical design tools and methodology including but not limited to physically aware synthesis and place & route tools and flows, extraction, and other analysis flows, and physical design verification (LEC, DVS, etc.)
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